S3C2440 Clock Architecture and Programming

If the CPU is the brain of the computer and the current is the blood of the computer, then the clock is the heart of the computer. The clock frequency determines the speed of the processor's calculations. Each of its "beats" drives the processor to continuously execute commands. The difference is that the heart rate of each part of the human body is the same, but the computer has multiple frequencies, and each part may have a different frequency. For example, the "brain" has one frequency, the "hand" has one frequency, and the "foot" uses another frequency. This raises two questions: How to generate these different frequencies? How does the processor interact with peripherals with different frequencies?

How are these different frequencies generated?

In order to obtain a stable clock, we generally use an external crystal oscillator. The crystal oscillator is composed of quartz and an oscillation circuit. The quartz can provide a stable frequency. Generally, a computer system requires at least one crystal oscillator. Some special peripherals also have their own unique crystal oscillators, such as network cards, graphics cards, etc. However, most peripherals connected to the CPU do not have their own crystal oscillators, so the CPU needs to provide them with clocks. However, different peripherals require different clocks. How does the CPU provide different clocks to these peripherals?

The S3C2440 processor mainly provides two connection buses for peripherals, the AHB bus (Advanced high Performance Bus) and the APB bus. The clocks of these two buses are the same before initialization, and the frequency is equal to the frequency provided by the external crystal oscillator. After initialization, they can provide different clocks for peripherals.

The contents of AHP and APB buses will be put in the later chapters as supplementary knowledge. Since the clocks of these two buses are different after initialization, the connected peripherals are also different. As shown in the figure below, some peripherals with higher working frequencies are connected to the AHB bus, such as memory, nandflash, LCD controller, etc., while peripherals with lower working frequencies are connected to the APB bus, such as UART serial port, Watchdog, GPIO, USB, etc. (Note: the word "connected" is used here because these devices can be unplugged without affecting the work of other peripherals).

We will not discuss how these peripherals are connected to the bus here, but we must first understand one thing: peripherals connected to the same bus will obtain the same clock.

The above picture is the clock generation diagram of s3c2440. It looks complicated, but it is not. You only need to understand the red framed part. However, if you want to write a UBS driver or a camera driver, you will be involved in the gray-green part of the picture. I will not go into details about the USB and cam parts here.

The red box in the figure represents the main clock generation process, the gray-green box represents the USB clock generation process, the red line represents the output HCLK, the green line represents PCLK, and the yellow line represents FCLK.

When uboot starts, you need to set the clock division. The purpose of the division is to generate three clocks: PCLK, FCLK and HCLK. PCLK is used for APB bus, HCLK is used for AHB bus, and FCLK is used for CPU. From the electrical parameters chapter of the datasheet, you can find that the maximum values ​​of FCLK, HCLK and PCLK are 400MHz, 100MHz and 50MHz respectively. Let's analyze how these three clocks are generated according to the steps in the figure. The following figure is a brief summary of the above figure:

1. Clock source

In order to reduce the electromagnetic interference of the external environment on the development board and reduce the production cost, the external crystal oscillator clock frequency of the development board is usually very low. As can be seen from the first red box in the figure, the CPU can be connected to two external clock sources, one is the oscillation clock source, and the other is the clock signal. The former is the quartz crystal oscillator circuit, and the latter is the clock signal generated by other oscillators, such as the clock signal generated by the signal generator. Although both are sine waveforms of specific frequencies, there are differences in the wiring methods of the CPU.

From this table, we can see that s3c2440 can connect two clock sources, one is the main clock source and the other is the USB clock source. If the main clock source needs to be connected to a crystal source, OM3 needs to be 0, that is, it needs to be grounded (UBS clock is not discussed here for the time being). Similarly, if the UBS clock source needs to be connected to a crystal source, OM2 needs to be grounded. From the circuit diagram, we can see that both OM2 and OM3 are grounded, and the XTIpll pin and XTOpll pin are connected to an external 12M crystal oscillator, so the clock source of the development board here is a 12M external crystal oscillator. (The USB clock source is not discussed here)

It should be noted that the clock provided by the crystal oscillator starts to oscillate only after power-on, while the signal clock provided externally is already oscillating when the board is not powered on, so a special treatment is required for the crystal oscillator clock source - frequency conversion locking.

2. Frequency conversion lock

When the development board is just powered on, the crystal oscillator OSC starts to provide the crystal oscillator clock. Since the system has just been powered on, the voltage signal is still unstable. At this time, the reset signal (nRESET) is pulled low, and the external crystal oscillator is directly used as the system clock FCLK. At this time, the FCLK is irregular. In order to let the CPU use a regular clock frequency, the clock needs to be disabled for a short period of time. This time is the Lock Time in the figure. During this period of time, the voltage will gradually stabilize, and the clock frequency will also be adjusted to a new stable state (VCO is adapted to new clock frequency). In addition, during this period of time, FCLK is 0, which means that the CPU will not run. When this Lock Time ends, FCLK will get a new frequency (FCLK is new frequency). Note that the FCLK frequency at this time is the frequency provided by the crystal oscillator. They are the same size. After multiplication, this value will change several times.

The following is the setting register for the frequency conversion lock time: bits 0 to 15 are used to set the main clock source lock time, and the last 15 bits are used to set the USB lock time, which is not considered here. It is worth noting that the corresponding lock time can be found in the electrical data table of the datasheet (PLL Lock Time).

3. Frequency multiplication setting (phase-locked loop)

When the CPU can obtain a stable clock, it needs to multiply the clock. Now we know that the clock input by the external crystal is 12M, so how to increase this clock to 100MHz or even 400MHz? This involves the second red box in the clock generation diagram (note the S, P, M above the box). This is called a phase-locked loop (PLL). The frequency multiplication operation of the main frequency is set by MPLL, while the frequency multiplication operation of USB is set by UPLL. UPLL will not be discussed for the time being. Therefore, in order to change the external clock and expand it to 400M, it is necessary to set the MPLLCON register.

As can be seen from the above figure, whether it is MLLCON or UPLLCON, it consists of three parts, the main frequency division, pre-division, and post-division control bits. These frequency division values ​​determine the frequency of 12M input and how much frequency will be output. The following table is the recommended settings in the manual: For example, if we want to multiply the 12M clock frequency to 405M, we need MDIV=0x7f, PDIV=0x2, SDIV=1. Note that 49M and 96M are set for USB UPPLCON.

Of course, you can also use the calculation formula without referring to this table:

4. Set the ratio (divider)

After setting the PLL register, when the stable clock passes through the phase-locked loop, it will output a larger multiple of the frequency, and this larger multiple of the frequency is FCLK. Now this value is 400MHz instead of 12MHz. Now we have the desired FCLK, so how do we get PCLK and HCLK? The following involves the setting of the divider.

How to set the values ​​of HDIVN and PCIVN, mainly look up the following table:

For example, if we want to set HCLK to 100 and PCLK to 50, then HCLK=FCLK/4, PCLK=FCLK/8. Looking up the table shows that it is 1:4:8, so HDIVN=0x2, PDIVN=0x1. dvin_UPLL is the UBS clock, which is not discussed here.

However, according to the datasheet, when HDIV is set to non-zero, the CPU bus mode needs to be changed. By default, FCLK=HCLK, and the CPU works in fast bus mode. After HDIV is set to non-zero, FCLK and HCLK are no longer equal. To change the CPU to asynchronous bus mode, the corresponding code needs to be used for setting.

So the code for the above three steps can be summarized as follows:

So the clock settings of S3C2440 are summarized as follows:

/* Set MPLL, FCLK : HCLK : PCLK = 400m : 100m : 50m */

/* LOCKTIME(0x4C000000) = 0xFFFFFFFF */

ldr r0, =0x4C000000

ldr r1, =0xFFFFFFFF

str r1, [r0]

/* CLKDIVN(0x4C000014) = 0X5, tFCLK:tHCLK:tPCLK = 1:4:8 */

ldr r0, =0x4C000014

ldr r1, =0x5

str r1, [r0]

/* Set the CPU to work in asynchronous mode */

mrc p15,0,r0,c1,c0,0

orr r0,r0,#0xc0000000 //R1_nF:OR:R1_iA

mcr p15,0,r0,c1,c0,0

/* Set MPLLCON(0x4C000004) = (92<<12)|(1<<4)|(1<<0) 

 * m = MDIV+8 = 92+8=100

 * p = PDIV+2 = 1+2 = 3

 * s = SDIV = 1

 * FCLK = 2*m*Fin/(p*2^s) = 2*100*12/(3*2^1)=400M

 */

ldr r0, =0x4C000004

ldr r1, =(92<<12)|(1<<4)|(1<<0)

str r1, [r0]

/* Once the PLL is set, the lock time will be locked until the PLL output is stable

 * Then the CPU operates at the new frequency FCLK