To correctly calculate the serial port baud rate, we must first understand the working principle of the chip clock. This part is written in detail in the s3c2410/s3c2440datasheet, but for novices, it is easier to understand by combining the TIMER and CLOCK experiments in Comrade Thisway's "s3c2410 Complete Development Process" and reading the materials while doing the experiments.
Here I will only talk about a problem that needs attention when calculating the value of the baud rate register UBRDIVn based on my own experience of failure.
The UBRDIVn register section on the datasheet says:
UART BAUD RATE DIVISOR REGISTER
There are three UART baud rate divisor registers including UBRDIV0, UBRDIV1 and UBRDIV2 in the UART block.
The value stored in the baud rate divisor register (UBRDIVn), is used to determine the serial Tx/Rx clock rate (baudrate) as follows:
UBRDIVn = (int)( UART clock / ( buffer rate x 16) ) –1
( UART clock: PCLK, FCLK/n or UEXTCLK )
Where, UBRDIVn should be from 1 to (216-1), but can be set zero only using the UEXTCLK which should be smaller than PCLK.
For example, if the baud-rate is 115200 bps and UART clock is 40 MHz, UBRDIVn is:
UBRDIVn = (int)(40000000 / (115200 x 16) ) -1
= (int)(21.7) -1 [round to the nearest whole number]
= 22 -1 = 21
In other words, as long as the UART clock is known, the value of UBRDIVn can be calculated. The following are respectively:
1. UEXTCLK
Check the manual: The UART can support bit rates up to 115.2K bps using system clock. If an external device provides the UART with UEXTCLK, then the UART can operate at higher speed. This means that when using the system clock (system clock), the UART baud rate can reach up to 115200, but if using this UEXTCLK (external clocks for the UART operation) serial port peripheral clock, you can set the baud rate above 115200.
2. PCLK and FCLK/n
There are two cases: using MPLL and not using MPLL
We know that the maximum frequency of s3c2410 can reach 266M, and the maximum frequency of s3c2440 can reach 533M, but the external crystal oscillator is usually only tens of MHz. How to turn tens of MHz into hundreds of MHz? This is the credit of MPLL.
The s3c2410 has two plls (phase locked loop, phase-locked loop, learned in high frequency, can achieve frequency multiplication, the high frequency of the s3c2410 is generated by this circuit). One of them is MPLL, M is main, which is used to generate three clock signals: Fclk (supply clock signal to the CPU core, the s3c2410 CPU main frequency we said is 200MHz, which refers to this clock signal, and accordingly, 1/Fclk is the CPU clock cycle), Hclk (supply clock signal to AHB bus peripherals, AHB is advanced high-performance bus), Pclk (supply clock signal to APB bus peripherals, APB is advanced peripherals bus). The peripherals connected to the AHB and APB buses are different. The AHB bus connects high-speed peripherals, and low-speed peripherals are interconnected through the APB bus. Obviously, different clock signals should be used for peripherals on different buses, AHB bus corresponds to Hclk, APB bus corresponds to Pclk. So you should figure out in advance which peripherals correspond to each bus, so that after setting the clock signal, the initialization value of the corresponding peripheral should be determined accordingly.
When MPLL is not used (i.e. MPLLCON register is not set), the external crystal oscillator is directly used as the system clock. Generally, there are two external crystal oscillators, one for the system clock, which is 12MHz (or other, determined by the specific board); the other for the real-time clock (RTC, real time clock, sends or sets various data of the clock and calendar according to the requirements of the CPU), which is 32.768KHz. At this time, PCLK is 12MHz.
When using MPLL, FCLK, HCLK and PCLK are obtained by setting the registers MPLLCON and CLKDIVN.
Get the UART clock (PCLK, FCLK/n or UEXTCLK) according to the formula
UBRDIVn = (int)( UART clock / ( buffer rate x 16) ) –1
It is easy to calculate.
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