s3c2440 bare metal system clock and timer settings

⑴Analysis of system clock principle

The clock determines the execution speed of 2440. 2440 can use an external clock source, or use an external crystal oscillator and then obtain the clock frequency through the internal crystal oscillator. See the figure below for specific selection of clock source:

The development board generally connects pins M2 and M3 to GND, so all of them use crystal oscillators.

In addition, 2440 provides three clock sources: FCLK (for CPU core), HCLK (advanced high performance bus, for AHB bus devices, such as CPU core, DMA, USB, etc.), PCLK (advanced performance bus, for peripheral devices, such as watchdog, PWM timer, ADC, etc.). For the phase-locked loop, 2440 has two PLLs, one of which is UPLL, which is dedicated to USB devices, and the other is MPLL for setting fclk, hclk, and pclk.

If PLL is not set, FCLK is Fin, that is, the external crystal oscillator is 12M.

After setting the PLL, you need to set the corresponding registers to get the required value. S3C2440 uses three frequency multiplication factors MDIV, PDIV and SDIV to set the frequency multiplication. The frequency multiplication factors can be set through registers MPLLCON and UPLLCON. The MPLLCON register is used to set the processor core clock frequency FCLK. The relationship between its input and output frequencies is as follows:

  FCLK=MPLL=(2*m*Fin)/(p*2^s)

Where m=(MDIV+8), p=(PDIV+2), s=SDIV.

The UPLLCON register is used to generate 48MHz or 96MHz and provide the USB clock (UCLK). The relationship between the input and output frequencies is:

UCLK=UPLL=(m *Fin) / (p * 2^s)

Where m=(MDIV+8), p=(PDIV+2), s=SDIV.

The relationship between the above MPLLCON and UPLLCON and MDIV, PDIV, SDIV is:

That is, bit 01 of PLLCON is SDIV, bits 4-9 are PDIV, and bits 12-19 are MDIV.

For convenience, the 2440 chip manual gives the reference setting PLL value:

Assuming the crystal oscillator is 12M, you can refer to the setting values ​​in the blue darkened part of the above figure. The 48M and 96M in the above figure are used to set UPLLCLK.

The FCLK setting can be completed through the table. As mentioned earlier, in addition to FCLK, HCLK and PCLK need to be set. Next, HCLK and PCLK can be set. At this time, two registers are required:

For CLKDIVN

The corresponding HCLK and PCLK can be obtained through this register. However, since the 8th and 9th bits of CAMDIVN are needed when setting HDIVN (that is, the 1st and 2nd bits of CLKDIVN), the CAMDIVN register is:

Combining the two registers above, we can get the frequency. From the two tables above, we can get four values: HDIVN, PDIVN, HCLK3_HALF and HCLK4_HALF. To describe their relationship, please refer to the table:

The following note about the clock is found at the back of the manual:

This means that if HDIVN is not 0, add:

mrcp15,0,r0,c1,c0,0

orr r0,r0,#R1_nF:OR:R1_iA

mcr p15,0,r0,c1,c0,0

The above settings can complete the setting of FCLK, HCLK, and PCLK. In fact, the operating status of 2440 before and after setting the clock is as follows: (The process diagram of setting MPLL is given below (UPLL is similar))

From the above figure, we can see that after a period of time after power-on, after waiting for the nRESET signal (reset signal) to return to a high level, we can then perform operations on the PLL registers. OSC is the frequency of the crystal oscillator, which is 12M, and VCO is the output frequency. We can also see that after setting the PLL, we need to wait for a period of time before we can output the set frequency. This waiting time can be set through the LOCKTIME register. This time needs to meet a certain minimum value, and the default value can be used. See the following figure for the description of this register:

Summarize:

Setting the clock is relatively simple. Here is the setting process:

1. Set the interval time for the CPU to go from the new clock frequency to the old frequency, set LOCKTIME (the default value is fine)

2. Set the FCLK, HCLK, PCLK frequency ratio. You can set the register CLKDIVN to assist CAMDIVN

3. /* If HDIVN in CLKDIVN is not 0, the CPU bus mode should be changed from "fast bus mode" to "asynchronous bus mode" */

_asm__(

 "mrc p15, 0, r1, c1, c0,0n" /* Read control register */

 "orr r1, r1,#0xc0000000n" /* Set to "asynchronous bus mode" */

 "mcr p15, 0, r1, c1, c0, 0n" /* Write control register */

 );

4. Set the FCLK clock according to personal requirements by setting MPLLCON

5. If necessary, set the UCLK clock, which can be set by setting UPLLCON

Test setup code:

void mpll_init(void )

{

//1. Set the interval time for the CPU to go from the new clock frequency to the old frequency. Set LOCKTIME (the default value is sufficient)

//2. Set the FCLK, HCLK, PCLK frequency ratio by setting the register CLKDIVN CAMDIVN

//If FCLK is set to 400M, HCLK=100M and PCLK=50M

//hdivn=2 pdivn=1

rCLKDIVN |= (2<<1) | 1;

rCAMDIVN &=~(1<<9);

//3. /*If HDIVN in CLKDIVN is not 0, the CPU bus mode should be changed from "fast bus mode" to "asynchronous bus mode" */

__asm{

  mrc p15, 0, r1, c1, c0, 0 /* Read control register */

  orr r1, r1, #0xc0000000 /* Set to "asynchronous bus mode" */

  mcr p15, 0, r1, c1, c0, 0 /* Write control register */

 };

// MMU_SetAsyncBusMode();

//4. Set the FCLK clock according to personal requirements by setting MPLLCON

 // FCLK=MPLL=(2*m*Fin)/(p*2^s)

 // Where m=(MDIV+8), p=(PDIV+2), s=SDIV

 // MDIV=0X5C PDIV=1 SDIV=1 FCLK=400M

 //

rMPLLCON=((0x5c<<12) | (1<<4) | 1);

//5. If necessary, set the UCLK clock, which can be set by setting UPLLCON

}

⑵Analysis of timer principle

The s3c2440 has five 16-bit timers: Timer0, 1, 2, 3, and 4. Timer0, 1, 2, and 3 have Pulse Width Modulation (PWM) function. Timer4 pin has no output. Timer0 is special and has a dead zone generator suitable for large currents.

Timers 0 and 1 share an 8-bit prescaler (prescaler), and timers 2, 3, and 4 share another 8-bit prescaler. The structure diagram is shown in the figure:

It can be seen that the clock source of the timer is PCLK, which first passes through the pre-divider to reduce the frequency and then enters the second frequency division. It can generate 5 different frequency division signals (1/2, 1/4, 1/8, 1/16 and external clocks TCLK0 and TCLK1.

These two prescalers can be set using the TCFG0 register, and their functions are shown in the figure:

As you can see, bits 0-7 of TCFG0 set divider 0, which is used to control timer 0 and timer 1, and bits 8 to 15 are used to set prescaler 1, which is used to control timer 2, 3, and 4. The frequency calculation formula is:

Timer clock frequency = PCLK / {prescaler value+1 } / {divider value}

The size of the prescaler value is the 8-bit size of the register setting above, which is 0 to 255. The size of the divider value is set by TCFG1 and can be 2, 4, 8, or 16. See the figure below:

After setting the clock through the above two registers, you can control the timer, including whether to turn on the timer, the time of the timer, etc.

First, we need to see TCON, which is used to control the opening and closing of the timer and whether to automatically reload the initial value:

The above table can be used to control 5 timers. When manually loading the timer value, you need to pay attention to the fact that you need to clear it to zero each time you rewrite the initial value. Taking timer3 as an example, the function of each bit is introduced as follows:

Timer 3 auto reload on/off This indicates whether the timer automatically reloads the timing time, or whether the timer is periodic.

Timer 3 output inverter on/off This indicates whether the reverse mode is enabled. The effect of enabling or not is:

Timer 3 manualupdate: Setting this bit to 1 manually loads data into TCNTB3 & TCMPB3 (these two registers will be introduced below).

Timer 3 start/stop Start or stop timer 3.

Before turning on the timer, you need to load the initial value into the timer to determine the time when the timer is triggered. Two registers are needed here: TCMPBn and TCNTBn. Here we take timer 0 as an example. Let's take a look at the register introduction first:

From the table above, we can see that TCMPBn is used to set the comparison value and TCNTBn is used to set the initial value. After setting these two registers, the timer will start to count down by 1 at the specified frequency, until it decreases to the comparison value set by TCMPBn. At this time, the value of TCNTBn can be observed by reading TCNTOn.

Use the timer settings as follows:

1. Select timer0-5 and set prescaler TCFG0 and divider TCFG1

2. Set the timing time for the timer, that is, load the initial value into TCNTB0 and load the TCMPBn register comparator (default 0)

3. Set the timer loading mode and open the timer using register TCON  

Timer setting reference code:

/*

void timer0_init()

{

//1. Select timer0-5 and set prescaler TCFG0 and divider TCFG1

    //Timer clock frequency = PCLK / {prescaler value+1 } / {divider value}

// PCLK=50m {prescaler value+1} / {divider value}

   rTCFG0 &= ~(0xFF) ;

     rTCFG0 |= 99 ; //Pre-scaling factor is 99

     rTCFG1 &= ~(0xf);

     rTCFG1 |= 0x03; //16 division

     //Timer clock frequency = 50000000/100/16 = 31250

//2. Set the timing time for the timer, that is, load the initial value into TCNTB0 and load the TCMPBn register comparator (default 0)

     rTCNTB0=31250;//once per second

//TCMPBn takes the default value 0

//3. Set the timing loading mode and open the timer using register TCON

     rTCON |= (1 << 1) ; // Load TCNTB0 and TCMPB0 into internal TCNT0 and TCMP0

     rTCON &=~(0xf);

     rTCON |= 0x09 ; //Automatically reload and turn on timer 0

     rINTMSK&=~(1<<10); //Open timer 0 interrupt

     timer0_service_Init(); //Interrupt service function initialization

}