STM32 learning: preliminary understanding of NVIC

1 Understanding of NVIC

      CM3 supports hardware interrupt nesting, which is divided into preemptive priority and sub-priority. The main usage rules are: the preemptive priority with a higher level can interrupt the lower level. When the preemptive priorities of the same level occur at the same time, the one with a higher priority will be interrupted first. If they are the same, they will occur in the order of hardware arrangement. If there is a sub-priority interrupt in progress, when other sub-priorities of the same level occur, they will be suspended first and executed after this interrupt is completed!

     Find the priority grouping pattern from the library function:

#define NVIC_PriorityGroup_0         ((uint32_t)0x700) /* 0 bits for pre-emption priority

                                                          4 bits for subpriority */

#define NVIC_PriorityGroup_1         ((uint32_t)0x600) /* 1 bits for pre-emption priority

                                                          3 bits for subpriority */

#define NVIC_PriorityGroup_2         ((uint32_t)0x500) /* 2 bits for pre-emption priority

                                                          2 bits for subpriority */

#define NVIC_PriorityGroup_3         ((uint32_t)0x400) /* 3 bits for pre-emption priority

                                                          1 bits for subpriority */

#define NVIC_PriorityGroup_4         ((uint32_t)0x300) /* 4 bits for pre-emption priority

                                                          0 bits for subpriority */

From this, we can see that the first group has only one level and 16 sub-priorities. I can understand it this way: if it is assigned to this group, nested interrupts cannot occur. When interrupts occur at the same time, the one with the highest sub-priority occurs first. If an interrupt is executed, the next interrupt can only be executed after the interrupt is executed. The last group is just the opposite. There are 15 levels. If an interrupt is executed, up to 15 interrupts can be nested to execute one interrupt. See the example below:

  NVIC_InitTypeDef NVIC_InitStructure; //Define interrupt initialization type structure variable

   NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1); //Configure priority group 1 2 preemptive priorities and 8 sub-priorities

  NVIC_InitStructure.NVIC_IRQChannel = EXTI0_IRQn; //Open external interrupt 0

  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; //Configure preemptive priority 0  

  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; //Sub-priority is configured as 0

  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; //Enable channel

  NVIC_Init(&NVIC_InitStructure); //Initialize the configuration of external interrupt 0

  NVIC_InitStructure.NVIC_IRQChannel = EXTI9_5_IRQn; //Open external interrupts 5 to 9

  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; //Configure preemptive priority 1  

  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1; //Sub-priority is configured as 1

  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; //Enable channel

  NVIC_Init(&NVIC_InitStructure); //Initialize the configuration of external interrupt 0

  NVIC_InitStructure.NVIC_IRQChannel = ADC1_2_IRQn; //ADC1中断

  NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; //Configure preemptive priority 1  

  NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1; //Sub-priority is configured as 1

  NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; //Enable channel

  NVIC_Init(&NVIC_InitStructure); //Initialize the configuration of external interrupt 0

From the above configuration, external interrupt 0 has the highest priority, which can interrupt ADC and external interrupts 5 to 9, that is, they can be nested. When the ADC interrupt and external interrupts 5 to 9 occur at the same time, their preemption priority levels are the same, and their sub-priority levels are also the same. Because the ADC1 hardware is ranked higher, the ADC interrupt occurs first. If any of the two interrupts is being executed, wait until the interrupt is executed before executing the other interrupt.