AVR MCU nRF24L01 send and receive driver

#include "iom16v.h"

#include "macros.h"

#include "12864.h"

//------------------------------------------------------------------------------

//spi flag

#define DDR_SPI DDRB

#define DD_MOSI 5

#define DD_MISO 6

#define DD_SCK 7

#define DD_SS 4

#define CE PB3

#define IRQ PB2

//--------------------------------NRF24L01 interface definition--------------------------------

//------------------------------------------------------------------------------

//#define NRF24L01_MISO PB6 //Input 0

#define Hign_24L01_MISO PORTB|=(1 << PB6)

#define Low_24L01_MISO PORTB &= ~(1 << PB6)

#define Read_24L01_MISO PINB & (1 << PB6)

//#define NRF24L01_MOSI PB5 //Output 1

#define Hign_24L01_MOSI PORTB |= (1 << PB5)

#define Low_24L01_MOSI PORTB &= ~(1 << PB5)

#define Read_24L01_MOSI PINB & (1 << PB5)

//#define NRF24L01_SCK PB7 //Output 1

#define Hign_24L01_SCK PORTB |= (1 << PB7)

#define Low_24L01_SCK PORTB &= ~(1 << PB7)

#define Read_24L01_SCK PINB & (1 << PB7);

//#define NRF24L01_CSN PB4 //Output 1

#define Low_24L01_CSN PORTB &= ~(1 << PB4)

#define Hign_24L01_CSN PORTB |= (1 << PB4)

//#define NRF24L01_CE PB3 //Output 1

#define Hign_24L01_CE PORTB |= (1 << PB3)

#define Low_24L01_CE PORTB &= ~(1 << PB3)

#define Read_24L01_CE PINB & (1 << PB3)

//*********************************************NRF24L01*************************************

#define TX_ADR_WIDTH 5 // Send address length, the maximum length is 5 5*8=40 bits

#define RX_ADR_WIDTH 5 // Receive address length

#define TX_PLOAD_WIDTH 32 // Send byte length,

#define RX_PLOAD_WIDTH 32 // Receive byte length

uchar TX_ADDRESS[TX_ADR_WIDTH]={0x34,0x43,0x10,0x10,0x01}; //Send address

uchar RX_ADDRESS[RX_ADR_WIDTH]={0x34,0x43,0x10,0x10,0x01}; //Receive address

//*******************************************NRF24L01 register instructions*******************************************************

#define READ_REG 0x00 // Read register instruction

#define WRITE_REG 0x20 // Write register instruction

#define RD_RX_PLOAD 0x61 // Read receive data instruction

#define WR_TX_PLOAD 0xA0 // Write data to be sent instruction

#define FLUSH_TX 0xE1 // Flush transmit FIFO instruction

#define FLUSH_RX 0xE2 // Flush receive FIFO instruction

#define REUSE_TX_PL 0xE3 // Define repeat loading data instruction

#define NOP 0xFF // Reserved

//****************************************SPI(nRF24L01) register address****************************************************

#define CONFIG 0x00 //Configure the receiving and sending status, CRC check mode and the receiving and sending status response method

#define EN_AA 0x01 //Auto answer function setting

#define EN_RXADDR 0x02 // Available channel settings

#define SETUP_AW 0x03 // Set the width of the receiving and sending address

#define SETUP_RETR 0x04 // Automatic resend function setting

#define RF_CH 0x05 // Operating frequency setting

#define RF_SETUP 0x06 // Transmit rate, power consumption function settings

#define STATUS 0x07 // Status register

#define OBSERVE_TX 0x08 // Send monitoring function

#define CD 0x09 // Address detection

#define RX_ADDR_P0 0x0A // Channel 0 receive data address

#define RX_ADDR_P1 0x0B // Channel 1 receive data address

#define RX_ADDR_P2 0x0C // Channel 2 receive data address

#define RX_ADDR_P3 0x0D // Channel 3 receive data address

#define RX_ADDR_P4 0x0E // Channel 4 receive data address

#define RX_ADDR_P5 0x0F // Channel 5 receive data address

#define TX_ADDR 0x10 // Transmit address register

#define RX_PW_P0 0x11 // Receive data length of receiving channel 0

#define RX_PW_P1 0x12 // Receive data length of receiving channel 0

#define RX_PW_P2 0x13 // Receive data length of receiving channel 0

#define RX_PW_P3 0x14 // Receive data length of receiving channel 0

#define RX_PW_P4 0x15 // Receive data length of receiving channel 0

#define RX_PW_P5 0x16 // Receive data length of receiving channel 0

#define FIFO_STATUS 0x17 // FIFO stack entry and exit status register settings

//*************************************************************

//*************************************************

//******* void spi_init() Initialize SPI

//**************************************************

void spi_init()

{

Hign_24L01_CSN;

DDR_SPI = (1<

DDR_SPI&=~((1<

SPCR=(1<

SPSR=0;

}

//**************************************************

//****** fly SPI_RW(fly date) dúxiěSPI

//**************************************************

fly SPI_RW(fly date)

{

SPDR=date;

while(!(SPSR&(1<

return SPDR;

}

//**************************************************

//*******uchar SPI_Read(uchar reg) read 24L01 register

//**************************************************

fly SPI_Read(fly reg)

{

fly reg_val;

Low_24L01_CSN;

SPI_RW(reg);

reg_val = SPI_RW(0);

Hign_24L01_CSN;

return(reg_val);

}

//**************************************************

//****** uchar SPI_RW_Reg(uchar reg, uchar value)

// Write 24L01 register

//**************************************************

uchar SPI_RW_Reg(uchar reg, uchar value)

{

flying status;

Low_24L01_CSN;

status = SPI_RW(reg);

SPI_RW(value);

Hign_24L01_CSN;

return(status);

}

//**************************************************

//****** fly SPI_Read_Buf(fly reg, fly *pBuf, fly bytes)

// Read 24L01 register BUFF

//**************************************************

uchar SPI_Read_Buf(uchar reg, uchar *pBuf, uchar bytes)

{

uint status1,uchar_ctr;

Low_24L01_CSN;

status1 = SPI_RW(reg);

for (fly_ctr=0; fly_ctr

pBuf[uchar_ctr] = SPI_RW(0);

Hign_24L01_CSN;

return(status1);

}

//**************************************************

//****** fly SPI_Write_Buf(fly reg, fly *pBuf, fly bytes)

// Write 24L01 register BUFF

//**************************************************

uchar SPI_Write_Buf(uchar reg, uchar *pBuf, uchar bytes)

{

flying status1, flying_ctr;

Low_24L01_CSN; //SPI enable

status1 = SPI_RW(reg);

for(fly_ctr=0; fly_ctr

SPI_RW(*pBuf++);

Hign_24L01_CSN; //Close SPI

return(status1); //

}

//**************************************************

//******* void SetRX_Mode(void)

//Receive mode settings

//**************************************************

void SetRX_Mode(void)

{

Low_24L01_CE;

SPI_Write_Buf(WRITE_REG + RX_ADDR_P0, RX_ADDRESS, RX_ADR_WIDTH); //Write receive address

SPI_RW_Reg(WRITE_REG + EN_AA, 0x01); //0 channel automatic response

SPI_RW_Reg(WRITE_REG + EN_RXADDR, 0x01); //Data channel 0

SPI_RW_Reg(WRITE_REG + RF_CH,0); //RF channel

SPI_RW_Reg(WRITE_REG + RX_PW_P0, RX_PLOAD_WIDTH); //Write channel 0 receives data length

SPI_RW_Reg(WRITE_REG + RF_SETUP, 0x07); //0db 1M

SPI_RW_Reg(WRITE_REG + CONFIG, 0x0f); //Receive mode

Hign_24L01_CE; //Start receiving

delayus(200); //Note that it cannot be too small

}

//**************************************************

//****** fly nRF24L01_RxPacket(fly* rx_buf)

// Receive data packets

//**************************************************

fly nRF24L01_RxPacket(fly* rx_buf)

{

uchar sta,flag=0;

sta=SPI_Read(STATUS); // Read the status register to determine the data receiving status

if(sta&0x40) // Check if data is received RX_DR==1?

{

Low_24L01_CE; //StandBy I mode

SPI_Read_Buf(RD_RX_PLOAD,rx_buf,TX_PLOAD_WIDTH);// read receive payload from RX_FIFO buffer

flag =1; //Read data completion flag

}

SPI_RW_Reg(WRITE_REG+STATUS,sta); //After receiving the data, RX_DR, TX_DS, MAX_PT are all set to 1, and the interrupt flag is cleared by writing 1

return (flag);

}

//**************************************************

//******* void nRF24L01_TxPacket(uchar * tx_buf)

// Send data packet

//**************************************************

void nRF24L01_TxPacket( uchar * tx_buf)

{

flying sta=0;

uchar flag=0;

Low_24L01_CE; //StandBy I mode

SPI_Write_Buf(WRITE_REG + TX_ADDR, TX_ADDRESS, TX_ADR_WIDTH);

SPI_Write_Buf(WRITE_REG + RX_ADDR_P0, TX_ADDRESS, TX_ADR_WIDTH); // Load the receiver address

SPI_Write_Buf(WR_TX_PLOAD, tx_buf, TX_PLOAD_WIDTH); // load data

SPI_RW_Reg(WRITE_REG + EN_AA, 0x01); //

SPI_RW_Reg(WRITE_REG + EN_RXADDR, 0x01); //

SPI_RW_Reg(WRITE_REG + SETUP_RETR, 0x1f); //500+86us

SPI_RW_Reg(WRITE_REG + RF_CH, 0); //

SPI_RW_Reg(WRITE_REG + RF_SETUP, 0x07); //

SPI_RW_Reg(WRITE_REG + CONFIG, 0x0e); // IRQ reception and transmission completion interrupt response, 16-bit CRC, master transmission

delayms(2);

Hign_24L01_CE; //Set CE high to trigger data transmission

delayus(10);

Low_24L01_CE;

}

void init_NRF24L01(void)

{

spi_init();

Low_24L01_CE; // Idle mode

Hign_24L01_CSN; // SPI off

Low_24L01_SCK; // Turn off the clock

}