Summary of the use of polarity and phase of MSP430 SPI

火辣西米秀

Summary of the use of polarity and phase of MSP430 SPI [Copy link]

The most common ways to write SPI polarity and phase are CPOL and CPHA, but there are also some other ways to write them, which are briefly summarized as follows:

SPI's CPOL indicates whether the SCLK level is low level 0 or high level 1 when it is idle:

CPOL=0, the clock level is low when idle, so when SCLK is valid, it is high, which is called active-high;

CPOL=1, the clock level is high when idle, so when SCLK is valid, it is low, which is called active-low;

Phase corresponds to the edge at which the data is sampled, the first edge or the second edge. 0 corresponds to the first edge and 1 corresponds to the second edge.

But the key point is that the description in MSP430 is different from the conventional one (see the description in the MSP430 user manual)

The program I configured SPI is as follows:

void SPI_init()
{
U0CTL =CHAR+SYNC+MM+SWRST; //8-bit SPI, SPI mode, host mode, keep in reset state
U0TCTL =CKPH+SSEL1+SSEL0+STC; //Clock source is MCLK, 3-wire mode;
U0BR0 =0x002;
U0BR1 =0x000; //Baud rate setting
U0MCTL =0x000; //No adjustment to the adjustment register;
ME1 =USPIE0; //Turn on SPI enable
U0CTL &=~SWRST; //Turn off reset
}

After experiment

U0TCTL =CKPH+SSEL1+SSEL0+STC;

U0TCTL =CKPL+SSEL1+SSEL0+STC;

Both configurations are OK.

The clock description in SST25V016B says that Mode0 and Mode3 are both supported.

Support CKPH CKPL

0 0

1 1

That is, choose both or neither

This is obviously inconsistent with the above results.