STM chip clock setting

All on-chip peripherals of the STM chip need to set the clock manually. Three different clock sources can be used to drive the system clock (SYSCLK): 

HSI oscillator clock: generated by an internal 8MHz RC oscillator, can be used directly as the system clock or as the PLL input after being divided by 2. The HSI RC oscillator can provide the system clock without any external devices. Its startup time is shorter than that of the HSE crystal oscillator. However, its clock frequency accuracy is still poor even after calibration. (So it is usually not used to provide SYSCLK) 

HSE oscillator clock: high-speed external clock signal, generated by HSE external crystal/ceramic resonator (more commonly used) or HSE user external clock 

PLL clock: clock source input, the internal PLL can be used to multiply the output clock of the HSI RC or the HSE crystal output clock. Once the PLL is activated, these parameters cannot be changed. 

Secondary clock sources: When not in use, each clock source can be independently enabled or disabled, thereby optimizing system power consumption. 

LSI clock: 40kHz low-speed internal RC, can be used to drive an independent watchdog and drive the RTC through program selection. RTC is used to automatically wake up the system from stop/standby mode 

LSE Clock: A 32.768kHz low speed external crystal can also be used to drive the RTC (RTCCLK) through program selection.

Clock configuration process: 

1. Reset the RCC register to the default value RCC_DeInit 

2. Turn on the external high-speed clock crystal HSE RCC_HSEConfig(RCC_HSE_ON); 

3. Wait for the external high-speed clock crystal to work HSEStartUpStatus =RCC_WaitForHSEStartUp();

4. Set AHB clock RCC_HCLKConfig; 

5. Set high-speed APB2 clock RCC_PCLK2Config; 

6. Set the low speed APB1 clock RCC_PCLK1Config 

7. Set PLL RCC_PLLConfig 

8. Enable PLL RCC_PLLCmd(ENABLE); 

9. Wait for PLL to work while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) 

10. Set the system clock RCC_SYSCLKConfig 

11. Determine whether PLL is the system clock while(RCC_GetSYSCLKSource() != 0x08) 

12. Turn on the peripheral clock to be used RCC_APB2PeriphClockCmd()/RCC_APB1PeriphClockCmd()

source code: 

void RCC_Configuration(void)   

{   

ErrorStatus HSEStartUpStatus;   

RCC_DeInit();                 

RCC_HSEConfig(RCC_HSE_ON);   

HSEStartUpStatus = RCC_WaitForHSEStartUp();   

if(HSESTartUpStatus == SUCCESS)   

{   

RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_16); //PLL input clock = HSE clock frequency; RCC_PLLMul_16——PLL input clock x 16; HSE = 4MHZ, so PLLCLK = 64MHZ   

RCC_HCLKConfig(RCC_SYSCLK_Div1); //RCC_SYSCLK_Div1——AHB clock = system clock (SYSCLK) = 64MHZ (external crystal oscillator 4HMZ)   

RCC_PCLK1Config(RCC_HCLK_Div2); //RCC_HCLK_Div2——APB1 clock = HCLK/2 = 32MHZ (external crystal oscillator 4HMZ)   

RCC_PCLK2Config(RCC_HCLK_Div1); //RCC_HCLK_Div1——APB2 clock = HCLK = 64MHZ (external crystal oscillator 4HMZ)   

//Note: AHB is mainly responsible for the external memory clock.   

// APB2 is responsible for AD, I/O, advanced TIM, serial port 1   

// APB1 is responsible for DA, USB, SPI, I2C, CAN, serial ports 2, 3, 4, 5, and common TIM   

FLASH_SetLatency(FLASH_Latency_2); //FLASH_Latency_1 1 delay cycle   

FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable); // Prefetch buffer enable   

RCC_PLLCmd(ENABLE);

while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)    

{   

} 

RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);

while(RCC_GetSYSCLKSource() != 0x08)    

{   

}   

}//end if(HSESStartUpStatus == SUCCESS)   

// Enables or disables the High Speed ​​APB(APB2) peripheral clock, APB2 peripheral clock enable   

RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |   

RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE, ENABLE);   

//Enables or disable the High Speed ​​APB(APB1) peripheral clock, APB1 peripheral clock enable   

RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);   

RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);   

RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);   

RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);   

}