Design of VGA Interface for Embedded System Based on S3C2410 and CH7004

　　1 Introduction

　　Embedded systems are widely used in various fields. One of the most common applications is embedded Linux intelligent terminal devices. In view of the application characteristics of the industrial control field, this type of device often integrates a control unit, a display keyboard unit, a data acquisition unit, a GPIO unit, and a communication unit (Ethernet, GPRS, serial port, etc.) to perform real-time data processing and control.

　　The terminal display of embedded systems tends to choose LCD displays. However, in the case of large-screen displays, large industrial-grade LCD displays are expensive. There are few choices. Adding a standard VGA interface to the embedded system can solve this problem well. There are many display devices that support the VGA interface and the price is relatively low, and the replacement of the display device will not affect the embedded system. The ARM9 device S3C2410 is widely used in embedded systems. Here we mainly introduce the VGA interface design of embedded systems based on CH7004 for this processor. The design scheme is simple in hardware design and software implementation, and the cost is low, thus providing a simple and effective large-screen image display solution for embedded devices.

　　2 VGA interface

　　Speaking of VGA interface, I believe many friends will be familiar with it, because this interface is the most important interface on computer monitors. Since the era of huge CRT monitors, VGA interface has been used and has been used till now. In addition, VGA interface is also called D-Sub interface. Many people think that only HDMI interface can transmit high-definition signals, but this is a misunderstanding that everyone can easily fall into, because VGA connection can also display 1080P images, and even the resolution can reach higher, so there is no problem in using it to connect display devices to watch high-definition videos, and although it is an analog interface, because VGA decomposes the video signal into three primary colors of R, G, B and HV horizontal and field signals for transmission, the loss in transmission is still quite small.

　　(1) VGA interface pinout Table 1 is a list of pin signal definitions for the 15-pin VGA interface.

　　(2) VGA interface timing VGA interface has multiple timings. When applying, different timings should be selected according to specific needs.

　　3 LCD controller internal control registers

　　LCD is the abbreviation of Liquid Crystal Display. The structure of LCD is to place liquid crystals between two parallel pieces of glass. There are many vertical and horizontal fine wires between the two pieces of glass. The direction of the rod-shaped crystal molecules is controlled by whether they are powered on or not, and the light is refracted to produce the picture. It considers the pollution prevention requirements of the entire life cycle of product development (including product design, extraction of raw materials, manufacturing, packaging, sales and use of products, and recycling and disposal after use) from the perspective of product performance, environmental protection, and economic feasibility. It uses resources and energy at multiple levels to reduce the impact of product production and consumption on the environment so that it is consistent with the carrying capacity of the earth.

　　There are 5 control registers inside the LCD controller: LCDCON1~LCD-CON5. LCDCON1 controls the pixel clock, scanning mode and color mode; LCDCON2 controls the frame synchronization pulse width, the number of valid lines in the frame and the number of invalid lines before and after the frame synchronization: LCDCON3 mainly controls the number of valid pixels in the line and the number of invalid pixels before and after the line synchronization: LCDCON4 mainly controls the line synchronization pulse width: LCDCON5 mainly controls the line and field synchronization pulses and data valid signal polarity, 16-bit color format. Relationship between data output and pixel clock jump.

　　3.1 CH7004 Device Introduction

　　CH7004 is a digital-to-analog video encoder produced by Chrontel. Its internal encoder supports NSTL and PAL video formats. The universal digital input interface supports 8, 12, 15, 16 and 24-bit digital RGB or YCrCb format input and 5 image resolutions. It integrates 3 independent high-speed video digital-to-analog converters, which can be controlled by users to output analog RGB or YUV. It provides an I2C interface for users to control the device working mode.

　　4 VGA interface design

　　The LCD controller of the S3C2410 processor is used to generate image data, VGA interface timing (640x480, 60 Hz) and configure the working mode of CH7004. CH7004 simulates the digital image data and finally generates analog image signals for display on the monitor supporting VGA interface. The hardware connection of VGA interface is shown in Figure 2.

　　The (640x480, 60 Hz) mode is chosen here based on practical needs and hardware characteristics: (1) The image size in embedded systems is mostly lower than 640x480, and this VGA mode display will not lose any original image information. (2) Each VGA display mode requires a different pixel clock, and the pixel clock of the S3C2410 internal LCD control is derived from the device's main frequency. Among the various divided pixel clocks, only 25.25 MHz (202 MHz main frequency divided by 8) is closest to the pixel clock 25.175 MHz required by the (640x480, 60 Hz) mode in the VGA mode. A slight pixel clock deviation will not affect the VGA interface display. (3) In the case of 16-bit color, the data stream bandwidth of the (640x480, 60 Hz) mode is 35.2 MB/s, so it will not block the S3C2410 data bus and will not affect other control and data processing operations of the processor.

　　The data input ports D0~D15 of CH7004 are connected to the corresponding data output ports of the LCD controller. The pixel clock VCLK of the LCD controller is input into CH7004 through the XCLK terminal. ADDR is low and the I2C bus address of CH7004 is set to 0x76. The impedance matching of the video signal needs to be considered at the output end of CH7004, otherwise problems such as image ghosting, snowflakes, or ripples on the edges will occur.

　　5 LCD controller and CH7004 configuration

　　5.1 LCD controller setup process

　　Set the LCD controller operating mode to (640x480, 60 Hz), 16-bit color (5:6:5), TFT mode.

　　(1) Set the system main clock (FCLK) to 202 MHz and the peripheral clock (HCLK) to 101 MHz;

　　(2) Set the LCD controller external port to TFT operation mode;

　　(3) Open up a continuous memory area of ​​600 KB (640x480x2 Bytes) for storing data;

　　(4) Set the control logic registers LCDCON1 to LCDCON5 of the LCD controller. LCDCON1: Set the pixel clock (VCLK) to be divided from the system main frequency by the frequency division factor CLKVAL = 1, the VM trigger rate is triggered every frame, the display mode is TFT, and the single pixel color bit number is 16 bits. Disable LCD controller data output and control signal generation ENVID=0; LCDCON2: Set invalid line number after frame synchronization VBPD=32, valid line number of frame LINEVAL=469; invalid line number before frame synchronization VFPD=9, frame synchronization width VSPW=1; LCDCON3: invalid pixel number after line synchronization HBPD=47, valid pixel number of line HOZVAL=639, invalid pixel number before line synchronization HFPD=15; LCDCON4: Line synchronization width HSPW=95; LCDCON5: The image storage mode in memory is set to little end storage BPP24BL=0.16-bit color image is 5:6:5 format FRM=1, pixel clock VCLK is set to the rising edge to transmit one pixel data, line synchronization pulse is set to negative pulse valid INVVUNE=1, frame synchronization pulse is set to negative pulse valid IN-VFRAME=1, LEND signal polarity is set to normal mode INVLEND=0, PWREN signal setting is valid setting PWREN=1, LEND signal output is allowed ENLEND=1.

　　(5) Allow video data output and timing control ENVID=1.

　　5.2 CH7004 working mode configuration

　　There are 25 working mode control registers inside CH7004C. There are 4 registers related to this design mode: Display Mode Register, Input Data Format Register, Clock Mode Register, Sync Polarity Register. By configuring the working mode control registers inside CH7004, CH7004 can work in accordance with the LCD controller.

　　Set the working mode of CH7004 to be consistent with the domestic LCD controller. The image size is 640x480, and the input data is in 16-bit 5:6:5 format. The data is sent directly to the internal D/A converter without passing through the standard encoder. The configuration sequence of CH7004 is as follows: (1) The Display Mode register is set to 640x480 display mode, and the selectable modes are 13~17. (2) The Input Data Format register is set to 16-bit color. RGB5:6:5 format, RGB signal bypass. Selecting the bypass mode allows the RGB input image signal to be directly sent to the D/A converter without passing through the video encoder. (3) The Clock Mode register is set to latch the image signal on the rising edge of the pixel clock. (4) The Sync Polarity register is set to enable the horizontal and vertical synchronization negative pulses. The horizontal and vertical synchronization signals are generated by the external processor and input to the V and H ports of CH7004. In actual operation, after the system is powered on, the processor only needs to configure the input data format register inside CH7004, and other registers directly use the reset default values.

　　5.3 CH7004 I2C bus configuration timing

　　The steps for S3C241O to configure the I2C bus of CH7004 are as follows: (1) First generate the CH7004 chip select address 0x76 and the read/write bit (0: write; 1: read) on the I2C bus; (2) Generate the on-chip offset address of a register; (3) Generate configuration data. After the PC controller completes an operation step, it must wait for the CH7004 to issue a correct operation response before continuing to the next operation. Figure 3 is the I2C read/write timing diagram of CH7004.

　　6 Testing and Conclusion

　　Experiments have shown that the color bar image has a good display effect on the monitor through the VGA interface. The VGA interface design method introduced uses the S3C2410 processor and the CH7004 video encoding device, which has the characteristics of simple hardware design, simple software implementation, and low price. It provides a simple and effective large-screen image display solution for embedded devices.