1 ;RCC register address image
2 RCC_BASE EQU 0x40021000
3 RCC_CR EQU (RCC_BASE + 0x00)
4 RCC_CFGR EQU (RCC_BASE + 0x04)
5 RCC_CIR EQU (RCC_BASE + 0x08)
6 RCC_APB2RSTR EQU (RCC_BASE + 0x0C)
7 RCC_APB1RSTR EQU (RCC_BASE + 0x10)
8 RCC_AHBENR EQU (RCC_BASE + 0x14)
9 RCC_APB2ENR EQU (RCC_BASE + 0x18)
10 RCC_APB1ENR EQU (RCC_BASE + 0x1C)
11 RCC_BDCR EQU (RCC_BASE + 0x20)
12 RCC_CSR EQU (RCC_BASE + 0x24)
13 ;GPIO register address image
14 GPIOC_BASE EQU 0x40011000
15 GPIOC_CRL EQU (GPIOC_BASE + 0x00)
16 GPIOC_CRH EQU (GPIOC_BASE + 0x04)
17 GPIOC_IDR EQU (GPIOC_BASE + 0x08)
18 GPIOC_ODR EQU (GPIOC_BASE + 0x0C)
19 GPIOC_BSRR EQU (GPIOC_BASE + 0x10)
20 GPIOC_BRR EQU (GPIOC_BASE + 0x14)
21 GPIOC_LCKR EQU (GPIOC_BASE + 0x18)
22 ;AFIO register address image
23 AFIO_BASE EQU 0x40010000
24 AFIO_EVCR EQU (AFIO_BASE + 0x00)
25 AFIO_MAPR EQU (AFIO_BASE + 0x04)
26 AFIO_EXTICR1 EQU (AFIO_BASE + 0x08)
27 AFIO_EXTICR2 EQU (AFIO_BASE + 0x0C)
28 AFIO_EXTICR3 EQU (AFIO_BASE + 0x10)
29 AFIO_EXTICR4 EQU (AFIO_BASE + 0x14)
30 ;NVIC register address image
31 NVIC_BASE EQU 0xE000E000
32 NVIC_SETEN EQU (NVIC_BASE + 0x0010) ; starting address of SETENA register array
33 NVIC_IRQPRI EQU (NVIC_BASE + 0x0400); starting address of interrupt priority register array
34 NVIC_VECTTBL EQU (NVIC_BASE + 0x0D08); Address of vector table offset register
35 NVIC_AIRCR EQU (NVIC_BASE + 0x0D0C); Address of application interrupt and reset control register
36
37 SETENA0 EQU 0xE000E100
38 SETENA1 EQU 0xE000E104
39 ;SysTick register address image
40 SysTick_BASE EQU 0xE000E010
41 SYSTICKCSR EQU (SysTick_BASE + 0x00)
42 SYSTICKRVR EQU (SysTick_BASE + 0x04)
43 ;;FLASH buffer register address image
44 FLASH_ACR EQU 0x40022000
45
46 ;SCB_BASE EQU (SCS_BASE + 0x0D00)
47 ;-----------------
48 MSP_TOP EQU 0x20005000 ; Main stack start value
49 PSP_TOP EQU 0x20004E00 ; process stack start value
50
51 BitAlias_BASE EQU 0x22000000 ; starting address of bit alias area
52 Flag1 EQU 0x20000200
53 b_flas EQU (BitAlias_BASE + (0x200*32) + (0*4)) ; bit address
54 b_05s EQU (BitAlias_BASE + (0x200*32) + (1*4)) ; bit address
55 DlyI EQU 0x20000204
56 DlyJ EQU 0x20000208
57 DlyK EQU 0x2000020C
58 SysTim EQU 0x20000210
59
60; Constant definition---------
61 Bit0 EQU 0x00000001
62 Bit1 EQU 0x00000002
63 Bit2 EQU 0x00000004
64 Bit3 EQU 0x00000008
65 Bit4 EQU 0x00000010
66 Bit5 EQU 0x00000020
67 Bit6 EQU 0x00000040
68 Bit7 EQU 0x00000080
69 Bit8 EQU 0x00000100
70 Bit9 EQU 0x00000200
71 Bit10 EQU 0x00000400
72 Bit11 EQU 0x00000800
73 Bit12 EQU 0x00001000
74 Bit13 EQU 0x00002000
75 Bit14 EQU 0x00004000
76 Bit15 EQU 0x00008000
77 Bit16 EQU 0x00010000
78 Bit17 EQU 0x00020000
79 Bit18 EQU 0x00040000
80 Bit19 EQU 0x00080000
81 Bit20 EQU 0x00100000
82 Bit21 EQU 0x00200000
83 Bit22 EQU 0x00400000
84 Bit23 EQU 0x00800000
85 Bit24 EQU 0x01000000
86 Bit25 EQU 0x02000000
87 Bit26 EQU 0x04000000
88 Bit27 EQU 0x08000000
89 Bit28 EQU 0x10000000
90 Bit29 EQU 0x20000000
91 Bit30 EQU 0x40000000
92 Bit31 EQU 0x80000000
93 ;Vector table************************************************************************************
94 AREA RESET, DATA, READONLY
95
96 DCD MSP_TOP ; Initialize the main stack
97 DCD Start ; Reset vector
98 DCD NMI_Handler ;NMI Handler
99 DCD HardFault_Handler ;Hard Fault Handler
100 DCD 0
101 DCD 0
102 DCD 0
103 DCD 0
104 DCD 0
105 DCD 0
106 DCD 0
107 DCD 0
108 DCD 0
109 DCD 0
110 DCD 0
111 DCD SysTick_Handler ; SysTick Handler
112 SPACE 200
113 ;***************************************************************************************
114 AREA |.text|, CODE, READONLY
115 ; Main program starts
116 ENTRY ; Indicates that the program starts executing from here
117 Start
118 ;Clock system settings
119 ; Start external 8M crystal oscillator
120 ldr r0,=RCC_CR
121 ldr r1,[r0]
122 orr1,#Bit16
123 str r1,[r0]
124 ClkOk
125 ldr r1,[r0]
126 ands r1,#Bit17
127 frog ClkOk
128 ldr r1,[r0]
129 orr1,#Bit17
130 str r1,[r0]
131 ;FLASH buffer
132 ldr r0,=FLASH_ACR
133 rice r1, #0x00000032
134 str r1,[r0]
135 ; Set the PLL phase-locked loop ratio to 7, and the HSE input is not divided
136 ldr r0,=RCC_CFGR
137 ldr r1,[r0]
138 orr r1,#Bit18 | Bit19 | Bit20 | Bit16 | Bit14
139 nose r1,#Bit10
140 str r1,[r0]
141 ;Start PLL phase-locked loop
142 ldr r0,=RCC_CR
143 ldr r1,[r0]
144 orr r1,#Bit24
145 str r1,[r0]
146 PllOk
147 ldr r1,[r0]
148 ands r1,#Bit25
149 frog PllOk
150 ;Select PLL clock as system clock
151 ldr r0,=RCC_CFGR
152 ldr r1,[r0]
153 orr r1,#Bit18 | Bit19 | Bit20 | Bit16 | Bit14
154 nose r1,#Bit10
155 orr1,#Bit1
156 str r1,[r0]
157 ;Other RCC related settings
158 ldr r0,=RCC_APB2ENR
159 mov r1,#Bit4
160 str r1,[r0]
161 ;IO port settings
162 ldr r0,=GPIOC_CRL
163 ldr r1,[r0]
164 orr r1,#Bit16 | Bit17 ; PC.4 output mode, maximum speed 50MHz
165 and r1,#~Bit18 & ~Bit19 ; PC.4 general push-pull output mode
166 str r1,[r0]
167 ;AFIO parameter settings
168
169 ;Systick parameter settings
170 ldr r0,=SYSTICKRVR ; Systick initial value
171 mov r1,#9000
172 str r1,[r0]
173 ldr r0,=SYSTICKCSR ; Set and start Systick
174 mov r1,#0x03
175 str r1,[r0]
176 ;NVIC
177 ;ldr r0,=SETENA0
178 ;move r1,0x00800000
179 ;str r1,[r0]
180 ;ldr r0,=SETENA1
181 ;mov r1,#0x00000100
182 ;str r1,[r0]
183 ;Switch to user-level line program mode
184 ldr r0,=PSP_TOP ; Initialize thread stack
185 msr psp,r0
186 mov r0,#3
187 msr control,r0
188 ; Initialize SRAM and registers
189 mov r1,#0
190 ldr r0,=Flag1
191 str r1,[r0]
192 ldr r0,=DlyI
193 str r1,[r0]
194 ldr r0,=DlyJ
195 str r1,[r0]
196 ldr r0,=DlyK
197 str r1,[r0]
198 ldr r0,=SysTim
199 str r1,[r0]
200 ;Main loop= ...
201 main
202 ldr r0,=Flag1
203 ldr r1,[r0]
204 tst r1,#Bit1 ;SysTick generates 0.5s
205 beq main ; The main program runs once every 0.5 seconds
206 ldr r0,=b_05s; bit-band operation clears the 0.5s flag
207 mov r1,#0
208 str r1,[r0]
209 bl LedFlas
210 b main
211 ;Subroutine********************************************************************************
212 LedFlas
213 push {r0-r3}
214 ldr r0,=Flag1
215 ldr r1,[r0]
216 tst r1,#Bit0
217 frog ONLED
218
219 ldr r0,=b_flas
220 mov r1,#0
221 str r1,[r0]
222 ;PC.4 output 1
223 ldr r0,=GPIOC_BRR
224 ldr r1,[r0]
225 orr r1,#Bit4
226 str r1,[r0]
227 b LedEx
228 ONLED
229 ldr r0,=b_flas
230 mov r1,#1
231 str r1,[r0]
232 ;PC.4 output 0
233 ldr r0,=GPIOC_BSRR
234 ldr r1,[r0]
235 orr r1,#Bit4
236 str r1,[r0]
237 LedEx
238 pop {r0-r3}
239 bx lr
240 ; Abnormal program **********************************************************************************
241 NMI_Handler
242 ;xxxxxxxxxxxxxxxxxx
243 bx lr
244 ;-----------------------------
245 HardFault_Handler
246 ;xxxxxxxxxxxxxxxxxx
247 bx lr
248 ;-----------------------------
249 SysTick_Handler
250 ldr r0,=SysTim
251 ldr r1,[r0]
252 add r1,#1
253 str r1,[r0]
254 cmp r1,#500
255 bcc TickExit
256 mov r1,#0
257 str r1,[r0]
258 ldr r0,=b_05s ; bit band operation set to 1
259 mov r1,#1
260 str r1,[r0]
261 TickExit
262 bx lr
263 ;***************************************************************************************
264 ALIGN ; Align the current position to a specified boundary by filling it with zeros or NOP instructions
265 ;-----------------------------
266 END
1 BIT5 EQU 0X00000020
2 BIT6 EQU 0X00000040
3 BIT7 EQU 0X00000080
4 BIT8 EQU 0X00000100
5 BIT9 EQU 0X00000200
6 BIT10 EQU 0X00000400
7 LED1 EQU BIT4 ;LED1--PD.8
8 LED2 EQU BIT9 ;LED2--PD.9
9 LED3 EQU BIT10 ;LED3--PD.10
10 GPIOD EQU 0X40011C00 ;GPIOD address
11 GPIOD_CRL EQU 0X40011C00 ; Low configuration register
12 GPIOD_CRH EQU 0X40011C04 ; High configuration register
13 GPIOD_ODR EQU 0X40011C0C ; output, offset address 0Ch
14 GPIOD_BSRR EQU 0X40011C10 ; low set, high clear offset address 10h
15 GPIOD_BRR EQU 0X40011C14 ; Clear, offset address 14h
16 IOPDEN EQU BIT7 ;GPIOD enable bit
17 RCC_APB2ENR EQU 0X40021018
18 ;STACK_TOP EQU 0X20002000
19
20 ;Stack initialization
21 Stack_Size EQU 0x00000400
22 AREA STACK, NOINIT, READWRITE, ALIGN=3
23 Stack_Mem SPACE Stack_Size
24 __initial_sp
25
26 Heap_Size EQU 0x00000200
27 AREA HEAP, NOINIT, READWRITE, ALIGN=3
28 __heap_base
29 Heap_Mem SPACE Heap_Size
30 __heap_limit
31
32; stack 8 bytes aligned
33 PRESERVE8
34 ; Use THUMB command
35 THUMB
36 ;Reset vector
37 AREA RESET,CODE,READONLY
38 ;DCD STACK_TOP ;MSP main stack pointer
39 ;DCD START ;Reset, PC initial value
40 __Vectors DCD __initial_sp ; Top of Stack
41 DCD Reset_Handler ; Reset Handler
42 DCD NMI_Handler ; NMI Handler
43 DCD HardFault_Handler ; Hard Fault Handler
44 DCD MemManage_Handler ; MPU Fault Handler
45 DCD BusFault_Handler ; Bus Fault Handler
46 DCD UsageFault_Handler ; Usage Fault Handler
47 DCD 0 ; Reserved
48 DCD 0 ; Reserved
49 DCD 0 ; Reserved
50 DCD 0 ; Reserved
51 DCD SVC_Handler ; SVCall Handler
52 DCD DebugMon_Handler ; Debug Monitor Handler
53 DCD 0 ; Reserved
54 DCD PendSV_Handler ; PendSV Handler
55 DCD SysTick_Handler ; SysTick Handler
56
57 ; External Interrupts
58 DCD WWDG_IRQHandler ; Window Watchdog
59 DCD PVD_IRQHandler ; PVD through EXTI Line detect
60 DCD TAMPER_IRQHandler ; Tamper
61 DCD RTC_IRQHandler ; RTC
62 DCD FLASH_IRQHandler ; Flash
63 DCD RCC_IRQHandler ; RCC
64 DCD EXTI0_IRQHandler ; EXTI Line 0
65 DCD EXTI1_IRQHandler ; EXIT Line 1
66 DCD EXTI2_IRQHandler ; EXTI Line 2
67 DCD EXTI3_IRQHandler ; EXTI Line 3
68 DCD EXTI4_IRQHandler ; EXTI Line 4
69 DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
70 DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
71 DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
72 DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
73 DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
74 DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
75 DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
76 DCD ADC1_2_IRQHandler ; ADC1 & ADC2
77 DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
78 DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
79 DCD CAN1_RX1_IRQHandler ; CAN1 RX1
80 DCD CAN1_SCE_IRQHandler ; CAN1 SCE
81 DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
82 DCD TIM1_BRK_IRQHandler ; TIM1 Break
83 DCD TIM1_UP_IRQHandler ; TIM1 Update
84 DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
85 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
86 DCD TIM2_IRQHandler ; TIM2
87 DCD TIM3_IRQHandler ; TIM3
88 DCD TIM4_IRQHandler ; TIM4
89 DCD I2C1_EV_IRQHandler ; I2C1 Event
90 DCD I2C1_ER_IRQHandler ; I2C1 Error
91 DCD I2C2_EV_IRQHandler ; I2C2 Event
92 DCD I2C2_ER_IRQHandler ; I2C2 Error
93 DCD SPI1_IRQHandler ; SPI1
94 DCD SPI2_IRQHandler ; SPI2
95 DCD USART1_IRQHandler ; USART1
96 DCD USART2_IRQHandler ; USART2
97 DCD USART3_IRQHandler ; USART3
98 DCD EXTI15_10_IRQHandler ; EXIT Line 15..10
99 DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
100 DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
101 DCD TIM8_BRK_IRQHandler ; TIM8 Break
102 DCD TIM8_UP_IRQHandler ; TIM8 Update
103 DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
104 DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
105 DCD ADC3_IRQHandler ; ADC3
106 DCD FSMC_IRQHandler ; FSMC
107 DCD SDIO_IRQHandler ; SDIO
108 DCD TIM5_IRQHandler ; TIM5
109 DCD SPI3_IRQHandler ; SPI3
110 DCD UART4_IRQHandler ; UART4
111 DCD UART5_IRQHandler ; UART5
112 DCD TIM6_IRQHandler ; TIM6
113 DCD TIM7_IRQHandler ; TIM7
114 DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
115 DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
116 DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
117 DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
118 __Vectors_End
119
120
121 AREA |.text|, CODE, READONLY
122 ENTRY ; Instructs to start execution
123 Reset_Handler
124 ;BL.W RCC_CONFIG_72MHZ
125 LDR R1,=RCC_APB2ENR
126 LDR R0,[R1] ; Read
127 LDR R2,=IOPDEN
128 ORR R0,R2 ;Change
129 STR R0, [R1] ; Write, enable GPIOD clock
130 ;LED1--PD.8 push-pull output, 50MHz
131 ;LED2--PD.9 push-pull output, 50MHz
132 ;LED3--PD.10 push-pull output, 50MHz
133 MOV R0,#0x333
134 LDR R1,=GPIOD_CRH; PD.8\9\10 are all in the high register
135 STR R0,[R1]
136
137 LDR R1,=GPIOD_ODR
138 LDR R2,=0x00000000
139 STR R2,[R1]
140 ;MOV R3,#1
141 B GOON
142 GOON
143 MOV R0,#1000
144 BL.W DELAY_NMS
145 LDR R1,=GPIOD_ODR
146 LDR R2,=0x0000FF00
147 STR R2,[R1]
148 MOV R0,#1000
149 BL.W DELAY_NMS
150 LDR R1,=GPIOD_ODR
151 LDR R2,=0x00000000
152 STR R2,[R1]
153
154 B GOON
155
156
157
158 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
159 ;;;RCC clock configuration HCLK=72MHz=HSE*9
160 ;;;PCLK2=HCLK PCLK1=HCLK/2
161 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
162 RCC_CONFIG_72MHZ
163 LDR R1,=0X40021000 ;RCC_CR
164 LDR R0,[R1]
165 LDR R2,=0X00010000 ;HSEON
166 ORR R0,R2
167 STR R0,[R1]
168 WAIT_HSE_RDY
169 LDR R2,=0X00020000 ;HSERDY
170 LDR R0,[R1]
171 ANDS R0,R2
172 CMP R0,#0
173 BEQ WAIT_HSE_RDY
174 LDR R1,=0X40022000 ;FLASH_ACR
175 MOV R0,#0X12
176 STR R0,[R1]
177 LDR R1,=0X40021004 ;RCC_CFGR clock configuration register
178 LDR R0,[R1]
179 ;PLL frequency multiplication factor, PCLK2, PCLK1 frequency division setting
180 ;HSE 9x frequency PCLK2=HCLK,PCLK1=HCLK/2
181 ;HCLK=72MHz 0x001D0400
182 ;HCLK=64MHz 0x00190400
183 ;HCLK=48MHz 0x00110400
184 ;HCLK=32MHz 0x00090400
185 ;HCLK=24MHz 0x00050400
186 ;HCLK=16MHz 0x00010400
187 LDR R2,=0x001D0400
188 ORR R0,R2
189 STR R0,[R1]
190 LDR R1,=0X40021000 ;RCC_CR
191 LDR R0,[R1]
192 LDR R2,=0X01000000 ;PLLON
193 ORR R0,R2
194 STR R0,[R1]
195 WAIT_PLL_RDY
196 LDR R2,=0X02000000 ;PLLRDY
197 LDR R0,[R1]
198 ANDS R0,R2
199 CMP R0,#0
200 BEQ WAIT_PLL_RDY
201 LDR R1,=0X40021004 ;RCC_CFGR
202 LDR R0,[R1]
203 MOV R2,#0X02
204 ORR R0,R2
205 STR R0,[R1]
206 WAIT_HCLK_USEPLL
207 LDR R0,[R1]
208 ANDS R0,#0X08
209 CMP R0,#0X08
210 BNE WAIT_HCLK_USEPLL
211 BX LR
212
213 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
214; Delay R0 (ms), error ((R0-1)*4+12)/8 us
215; When the delay is long, the error is less than 0.1%
216 DELAY_NMS
217 PUSH {R1} ; 2 cycles
218 DELAY_NMSLOOP
219 SUB R0,#1
220 MOV R1,#7200
221 DELAY_ONEUS
222 SUB R1,#1
223 NOP
224 NOP
225 NOP
226 CMP R1,#0
227 BNE DELAY_ONEUS
228 CMP R0,#0
229 BNE DELAY_NMSLOOP
230 POP {R1}
231 BX LR
232
233
234
235
236 ;Exception
237
238 NMI_Handler PROC
239 EXPORT NMI_Handler [WEAK]
240 B .
241 ENDP
242 HardFault_Handler\
243 PROC
244 EXPORT HardFault_Handler [WEAK]
245 B .
246 ENDP
247 MemManage_Handler\
248 PROC
249 EXPORT MemManage_Handler [WEAK]
250 B .
251 ENDP
252 BusFault_Handler\
253 PROC
254 EXPORT BusFault_Handler [WEAK]
255 B .
256 ENDP
257 UsageFault_Handler\
258 PROC
259 EXPORT UsageFault_Handler [WEAK]
260 B .
261 ENDP
262 SVC_Handler PROC
263 EXPORT SVC_Handler [WEAK]
264 B .
265 ENDP
266 DebugMon_Handler\
267 PROC
268 EXPORT DebugMon_Handler [WEAK]
269 B .
270 ENDP
271 PendSV_Handler PROC
272 EXPORT PendSV_Handler [WEAK]
273 B .
274 ENDP
275 SysTick_Handler PROC
276 EXPORT SysTick_Handler [WEAK]
277 B .
278 ENDP
279 ;Interrupt
280 Default_Handler PROC
281
282 EXPORT WWDG_IRQHandler [WEAK]
283 EXPORT PVD_IRQHandler [WEAK]
284 EXPORT TAMPER_IRQHandler [WEAK]
285 EXPORT RTC_IRQHandler [WEAK]
286 EXPORT FLASH_IRQHandler [WEAK]
287 EXPORT RCC_IRQHandler [WEAK]
288 EXPORT EXTI0_IRQHandler [WEAK]
289 EXPORT EXTI1_IRQHandler [WEAK]
290 EXPORT EXTI2_IRQHandler [WEAK]
291 EXPORT EXTI3_IRQHandler [WEAK]
292 EXPORT EXTI4_IRQHandler [WEAK]
293 EXPORT DMA1_Channel1_IRQHandler [WEAK]
294 EXPORT DMA1_Channel2_IRQHandler [WEAK]
295 EXPORT DMA1_Channel3_IRQHandler [WEAK]
296 EXPORT DMA1_Channel4_IRQHandler [WEAK]
297 EXPORT DMA1_Channel5_IRQHandler [WEAK]
298 EXPORT DMA1_Channel6_IRQHandler [WEAK]
299 EXPORT DMA1_Channel7_IRQHandler [WEAK]
300 EXPORT ADC1_2_IRQHandler [WEAK]
301 EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
302 EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
303 EXPORT CAN1_RX1_IRQHandler [WEAK]
304 EXPORT CAN1_SCE_IRQHandler [WEAK]
305 EXPORT EXTI9_5_IRQHandler [WEAK]
306 EXPORT TIM1_BRK_IRQHandler [WEAK]
307 EXPORT TIM1_UP_IRQHandler [WEAK]
308 EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
309 EXPORT TIM1_CC_IRQHandler [WEAK]
310 EXPORT TIM2_IRQHandler [WEAK]
311 EXPORT TIM3_IRQHandler [WEAK]
312 EXPORT TIM4_IRQHandler [WEAK]
313 EXPORT I2C1_EV_IRQHandler [WEAK]
314 EXPORT I2C1_ER_IRQHandler [WEAK]
315 EXPORT I2C2_EV_IRQHandler [WEAK]
316 EXPORT I2C2_ER_IRQHandler [WEAK]
317 EXPORT SPI1_IRQHandler [WEAK]
318 EXPORT SPI2_IRQHandler [WEAK]
319 EXPORT USART1_IRQHandler [WEAK]
320 EXPORT USART2_IRQHandler [WEAK]
321 EXPORT USART3_IRQHandler [WEAK]
322 EXPORT EXTI15_10_IRQHandler [WEAK]
323 EXPORT RTCAlarm_IRQHandler [WEAK]
324 EXPORT USBWakeUp_IRQHandler [WEAK]
325 EXPORT TIM8_BRK_IRQHandler [WEAK]
326 EXPORT TIM8_UP_IRQHandler [WEAK]
327 EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
328 EXPORT TIM8_CC_IRQHandler [WEAK]
329 EXPORT ADC3_IRQHandler [WEAK]
330 EXPORT FSMC_IRQHandler [WEAK]
331 EXPORT SDIO_IRQHandler [WEAK]
332 EXPORT TIM5_IRQHandler [WEAK]
333 EXPORT SPI3_IRQHandler [WEAK]
334 EXPORT UART4_IRQHandler [WEAK]
335 EXPORT UART5_IRQHandler [WEAK]
336 EXPORT TIM6_IRQHandler [WEAK]
337 EXPORT TIM7_IRQHandler [WEAK]
338 EXPORT DMA2_Channel1_IRQHandler [WEAK]
339 EXPORT DMA2_Channel2_IRQHandler [WEAK]
340 EXPORT DMA2_Channel3_IRQHandler [WEAK]
341 EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
342
343 WWDG_IRQHandler
344 PVD_IRQHandler
345 TAMPER_IRQHandler
346 RTC_IRQHandler
347 FLASH_IRQHandler
348 RCC_IRQHandler
349 EXTI0_IRQHandler
350 EXTI1_IRQHandler
351 EXTI2_IRQHandler
352 EXTI3_IRQHandler
353 EXTI4_IRQHandler
354 DMA1_Channel1_IRQHandler
355 DMA1_Channel2_IRQHandler
356 DMA1_Channel3_IRQHandler
357 DMA1_Channel4_IRQHandler
358 DMA1_Channel5_IRQHandler
359 DMA1_Channel6_IRQHandler
360 DMA1_Channel7_IRQHandler
361 ADC1_2_IRQHandler
362 USB_HP_CAN1_TX_IRQHandler
363 USB_LP_CAN1_RX0_IRQHandler
364 CAN1_RX1_IRQHandler
365 CAN1_SCE_IRQHandler
366 EXTI9_5_IRQHandler
367 TIM1_BRK_IRQHandler
368 TIM1_UP_IRQHandler
369 TIM1_TRG_COM_IRQHandler
370 TIM1_CC_IRQHandler
371 TIM2_IRQHandler
372 TIM3_IRQHandler
373 TIM4_IRQHandler
374 I2C1_EV_IRQHandler
375 I2C1_ER_IRQHandler
376 I2C2_EV_IRQHandler
377 I2C2_ER_IRQHandler
378 SPI1_IRQHandler
379 SPI2_IRQHandler
380 USART1_IRQHandler
381 USART2_IRQHandler
382 USART3_IRQHandler
383 EXTI15_10_IRQHandler
384 RTCAlarm_IRQHandler
385 USBWakeUp_IRQHandler
386 TIM8_BRK_IRQHandler
387 TIM8_UP_IRQHandler
388 TIM8_TRG_COM_IRQHandler
389 TIM8_CC_IRQHandler
390 ADC3_IRQHandler
391 FSMC_IRQHandler
392 SDIO_IRQHandler
393 TIM5_IRQHandler
394 SPI3_IRQHandler
395 UART4_IRQHandler
396 UART5_IRQHandler
397 TIM6_IRQHandler
398 TIM7_IRQHandler
399 DMA2_Channel1_IRQHandler
400 DMA2_Channel2_IRQHandler
401 DMA2_Channel3_IRQHandler
402 DMA2_Channel4_5_IRQHandler
403 B .
404
405 ENDP
406
407 ALIGN
408
409 END
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- Learn ARM development(20)With the previous Tick interrupt, the basic task switching conditions are ready. However, this "easterly" is also difficult to understand. Only through continuous practice can we understand it. ...
- Learn ARM development(19)After many days of hard work, I finally got the interrupt working. But in order to allow RTOS to use timer interrupts, what kind of interrupts can be implemented in S3C44B0? There are two methods in S3C44B0. ...
- Learn ARM development(14)
- Learn ARM development(15)
- Learn ARM development(16)
- Learn ARM development(17)
Professor at Beihang University, dedicated to promoting microcontrollers and embedded systems for over 20 years.
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