Introduction to STM32 input capture

     Input capture mode can be used to measure pulse width or frequency. Except for TIM6 and TIM7, all other STM32 timers have input capture function. Simply put, STM32 input capture detects the edge signal on TIMx_CHx. When the edge signal changes (such as rising edge/falling edge), the current timer value (TIMx_CNT) is stored in the capture/compare register (TIMx_CCRx) of the corresponding channel to complete a capture. At the same time, you can also configure whether to trigger interrupt/DMA during capture, etc.

     For example, we use TIM5_CH1 to capture the high-level pulse width, that is, we need to first set the input capture to rising edge detection and record the value of TIM5_CNT when the rising edge occurs. Then configure the capture signal to fall edge capture. When the falling edge arrives, capture occurs and record the TIM5_CNT value at this time. In this way, the difference between the two TIM5_CNTs is the high-level pulse width. At the same time, we know the counting frequency of TIM5, so we can calculate the exact time of the high-level pulse width.

     First, TIMx_ARR and TIMx_PSC, these two registers are used to set the automatic reload value and the clock division of TIMx.

     Let's take a look at the capture/compare mode register 1: TIMx_CCMR1. This register is very useful when capturing inputs. TIMx_CCMR1 is obviously configured for two channels. The lower eight bits [7:0] are used to control capture/compare channel 1, while the upper eight bits [15:8] are used to control capture/compare channel 2. Because TIMx also has the CCMR2 register, we can know that CCMR2 is used to control channel 3 and channel 4 (see page 290, section 14.4.8 of the STM32 Reference Manual for details).

    The capture/compare channel 1 of TIM5 is used here, and we focus on the [7:0] bits of TIMx_CMMR1 (in fact, the upper 8 bits are configured similarly).

    Let's take a look at the capture/compare enable register: TIMx_CCER;

    Next, let’s look at the DMA/interrupt enable register: TIMx_DIER. We need to use interrupts to process the captured data, so the capture compare interrupt of channel 1 must be enabled, that is, CC1IE is set to 1.

    Control register: TIMx_CR1, we only use its lowest bit, which is used to enable the timer;

    Finally, let's take a look at the capture/compare register 1: TIMx_CCR1. This register is used to store the value of TIMx_CNT when capture occurs. We can read the TIMx_CNT value of channel 1 at the moment of capture from TIMx_CCR1. Through the difference between two captures (one rising edge capture and one falling edge capture), we can calculate the width of the high-level pulse.  

    Enable capture and update interrupts (set the DIER register of TIM5) 

   Because we want to capture the pulse width of the high-level signal, the first capture is the rising edge, and the second capture is the falling edge. After capturing the rising edge, the capture edge must be set to the falling edge. At the same time, if the pulse width is long, the timer will overflow. The overflow must be processed, otherwise the result will be inaccurate. We do both of these things in the interrupt, so the capture interrupt and update interrupt must be enabled.

 1 void init_tim2_cam(u16 psc, u16 arr, u8 way, u8 dir)

 2 {

 3 RCC->APB1ENR |= 1 << 0; //Enable timer 2 clock

 4 RCC->APB2ENR |= 1 << 2; //Enable PortA

 5 

 6     switch (way)

 7 {

 8 case 1:

 9 GPIOA->CRL &= 0xfffffff0;

10 GPIOA->CRL |= 0x00000008; 

11 break;

12 case 2:

13 GPIOA->CRL &= 0xffffff00;

14 GPIOA->CRL |= 0x00000088;

15 break;

16 case 3:

17 GPIOA->CRL &= 0xfffff000;

18 GPIOA->CRL |= 0x00000888;

19 break;

20 case 4:

21 GPIOA->CRL &= 0xffff0000;

22 GPIOA->CRL |= 0x00008888;

23 break;

24 }

25 

26 TIMER->PSC = psc;

27 TIMER->ARR = arr;

28 

29 switch (way)

30 {

31 case 4:

32 TIMER->CCMR2 |= 1 << 8;

33 if (dir == 0)

34 TIMER->CCER |= 1 << 13; //Falling edge capture

35 else 

36 TIMER->CCER &= ~(1 << 13); // rising edge capture

37 TIMER->CCER |= 1 << 12;

38 TIMER->DIER |= 1 << 4;

39 case 3: //CCR3 PA2

40 TIMER->CCMR2 |= 1 << 0;

41 if (dir == 0)

42 TIMER->CCER |= 1 << 9; //Falling edge capture

43 else 

44 TIMER->CCER &= ~(1 << 9); // rising edge capture

45 TIMER->CCER |= 1 << 8;

46 TIMER->DIER |= 1 << 3; 

47 case 2: //CCR2 PA1

48 TIMER->CCMR1 |= 1 << 8; //CCR2 configuration channel direction: input

49 if (dir == 0)

50 TIMER->CCER |= 1 << 5; //Falling edge capture

51 else 

52 TIMER->CCER &= ~(1 << 5); // rising edge capture

53 TIMER->CCER |= 1 << 4; //CCR2 channel capture enable

54 TIMER->DIER |= 1 << 2; //CCR2 channel allows capture interrupt

55 case 1: //>CCR1 PA0

56 TIMER->CCMR1 |= 1 << 0; //CCR1 configuration channel direction: input

57 if (dir == 0)

58 TIMER->CCER |= 1 << 1; //Falling edge capture

59 else 

60 TIMER->CCER &= ~(1 << 1); // rising edge capture

61 TIMER->CCER |= 1 << 0; //CCR1 capture enable

62 TIMER->DIER |= 1 << 1; //CCR1 channel allows capture interrupt

63 break;

64 }

65 TIMER->DIER |= 1 << 0; //Enable update interrupt

66 MY_NVIC_Init(1, 2, TIM2_IRQChannel, 2); //Interrupt

67 TIMER->CR1 = 0x01; // Enable timer

68 TIMER->SR &= ~(1 << 0);

69 }