The main features of the s3c2410 storage controller are as follows:
1. Big-endian/little-endian mode can be set through software.
2. Divided into 8 banks, each bank is 128M, a total of 1G.
3. The data width of each bank can be set to 8/16/32 bits (except bank0, because bank0 is used for system boot)
4. Bank0-5 supports ROM SRAM, etc., bank6-7 supports ROM SRAM, SDRAM, etc.
5. The starting address space of bank0-6 is fixed, and bank7 is variable.
6. The space size of bank6-7 can be adjusted
7. The access timing of all banks can be programmed.
8. External wait mode can be used to extend the access cycle.
9Support SDRAM self-refresh mode and power down mode test.
The space allocation is as follows:
When booting from nor flash, the space 0x00000000-0x08000000 is mapped to bank0 to read the initialization code. If booting from nand flash, the space is mapped to the 4k ROM on the chip. In addition, the space allocation of bank6-bank7 is as follows:
(Note: the space size of bank6-7 must be consistent)
(See next section)
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