About Watchdog of s3c2410

1. Watchdog principle

Watchdog is essentially a timer. The timer counts the clock. When the timer overflows, a reset signal is generated to reset the entire system. In a program or embedded system, the watchdog timer needs to be reset and re-counted regularly. The timer will not overflow and reset the system, thus ensuring the normal operation of the system. When some reason (such as interference) causes the program to run away or enter an infinite loop, the program cannot reset the watchdog timer regularly, and the count overflow generates a reset signal, causing the system to reset.

Suppose the time for a complete running cycle of the system program is T1, the timing cycle of the watchdog is T2, T2>T1, and the count value of the timer is modified after the program runs for one cycle. As long as the program runs normally, the timer will not overflow. If the program "runs away" or enters an infinite loop, the system cannot modify the count value of the time at T1, and keeps counting until it overflows at T2, triggering a system reset and making the system run again, thereby playing a monitoring role.

From the above explanation, it can be seen that the role of Watchdog is to prevent the system from accidentally "running away" and causing the entire system to crash, and to restore (reset) the system operation.

2. S3C2410 watchdog control

1) Used as a regular timer and can generate interrupts

2) Used as a watchdog timer, it can generate a reset signal of 128 clock cycles when it expires

Specifically, see the figure below: the input clock is PCLK (the clock frequency is equal to the main frequency of the system), which undergoes two levels of frequency division (Prescaler and frequency division factor), and finally the divided clock is used as the input clock of the timer. When the counter expires, an interrupt or reset signal can be generated.

The calculation formula of the watchdog timer count value is as follows:

1) The clock cycle input to the counter

t_watchdog = 1/( PCLK / (Prescaler value + 1) / Division_factor )

The values ​​of the prescaler and the division factor are set by the user in WTCON (watchdog clock control register).

2) Watchdog timing cycle

   T = count value (WTCNT initial value - WTCNT current value) * t_watchdog

WTCNT is the watchdog data register, which is used to set the number of clock cycles to count. Multiplying by the clock cycle is the total timing time.