Design of embedded gateway circuit based on CAN bus and Ethernet

　　A method for interconnecting industrial fieldbus and Ethernet is proposed, and the design and implementation of the protocol conversion gateway between Ethernet and CAN fieldbus are introduced. AT89C55 is used as the main processor, and the interconnection between CAN bus and Ethernet is realized through two interface chips. The hardware structure and software design ideas are given respectively. This provides a feasible method for the integration of enterprise information network and control network.

　　Ethernet interface module: The system selected the AT89C55 single-chip computer produced by Atmel with relatively high performance and price. It is oriented to measurement and control objects and embedded applications, so its architecture, CPU, instruction system, and peripheral unit circuits are specially designed according to this requirement. It has an internal FLASH program memory of up to 20 KB. The AT89C55 is fully compatible with the 8051 instruction set. The on-chip FLASH facilitates users to perform online programming. The working speed can reach up to 33 MHz, 256 B of internal RAM, 32 programmable I/O ports, 3 16-bit timers/counters, 8 interrupt sources, and supports low-power idle working mode. The Ethernet interface uses the RTL8019AS chip, which is a highly integrated Ethernet controller produced by Realtek, which can realize all the functions of the Ethernet media access layer (MAC) and physical layer (PHY). There are two RAM areas inside RTL8019AS: one is 16 KB, with addresses of 0x4000~0x7fff. To receive and send data packets, the 16 KB RAM inside RTL8019AS must be read and written through DMA. It is actually a dual-port RAM, that is, there are two buses connected to it, one bus is used for RTL8019AS to read/write or write/read the RAM, that is, local DMA; the other bus is used for the microcontroller to read or write the RAM, that is, remote DMA; the second is 32 bytes, with addresses of 0x0000~0x001F, used to store Ethernet physical addresses. The hardware interface schematic diagram of the main control chip and the Ethernet interface chip is shown in Figure 2. It is worth noting that since the maximum Ethernet packet can exceed 1,500 bytes, the on-chip RAM of AT89C55 is only 256 bytes, so it cannot store such a large packet, so a 32 KB external RAM is extended here, which can also improve the data transmission speed of the microcontroller.

　　CAN interface module: The main components of the CAN system are the CAN controller and the transceiver. In this design, the CAN interface module uses the SJA1000 chip and the PCA82C250 chip. The SJA1000 is an independent CAN controller. It is a replacement for another CAN controller PCA82C200 from Philips and adds a new working mode (Peli CAN) that supports the CAN 2.0B protocol. The SJA1000 mainly completes the CAN communication protocol, realizes the assembly and splitting of messages, the filtering and verification of received information, etc.

　　PCA82C250 is the interface between the CAN controller and the physical bus, and is mainly used to enhance the system's driving capability. In a system using a transceiver, the number of nodes can reach at least 110, while also having the ability to reduce radio frequency interference (RFI) and strong anti-electromagnetic interference (EMI). When processing this part of the circuit, there are several places to pay special attention to:

　　(1) Problem with the crystal oscillator circuit. Both the 89C55 and SJA1000 should have their own independent crystal oscillator circuits, and the clock output signal CLKOUT of the SJA1000 cannot be used to drive the microcontroller.

　　(2) The reset pin problem. Although the reset of SJA1000 is low level, it cannot be directly connected to the reset pin of the microcontroller through a NOT gate. Generally, there are two ways to solve the reset pin problem: the first is to use the I/O pin of the microcontroller to control the reset pin of SJA. The advantage is that the microcontroller can fully control the reset process of SJA; the second is to use an appropriate reset chip. In order to reduce costs, this design adopts the first method.

　　(3) The potential of the RX1 pin must be maintained at approximately 0.5 VCC, otherwise the logic level required by the CAN protocol cannot be formed.

　　(4) Pay attention to the terminal impedance matching of the cable, which directly affects whether the CAN bus can work normally and the network performance. The hardware circuit diagram of the CAN interface module is shown in Figure 3. A slope resistor R is connected to the RS pin of PCA82C250. The size of the resistor can be adjusted appropriately according to the bus communication speed.