Design of DMA interface based on MPC8260 and FPGA

Introduction
　　In the design of a wireless communication signal detection platform based on software radio, the signal received by the antenna is processed by the frequency converter and A/D converted, and then sent to the main control board through the high-speed channel for data distribution and processing. The structural block diagram of the system is shown in Figure 1.

Figure 1 System structural block diagram of the main control board
　　The hardware core of the main control board is the embedded microprocessor MPC8260, which is responsible for loading system software, distributing data, and interacting with external command control. In terms of software, the high-performance VxWorks embedded real-time operating system is used. The RF signal received from the antenna is connected to the FPGA as a data source after frequency conversion and A/D conversion. After the FPGA performs pre-processing such as intermediate frequency conversion and channel estimation on the received data, the data is transferred to the local memory under the control of the CPU. Finally, the CPU packages the data for rapid distribution. Therefore, transmitting a high-speed data stream of 40 to 50 Mbps from the FPGA to the CPU becomes a key to system design.
　　If the CPU needs to intervene in each byte of data, then the data transmission rate will be very low regardless of whether it is interrupt-driven or program-queried, and it cannot meet the system requirements. Compared with the general program control transmission mode, DMA (direct memory access) has the advantages of high data transmission speed, short I/O response time and small CPU overhead. Therefore, the DMA transmission mode is selected so that the data in the FPGA can be directly stored in the local memory without passing through the CPU internal register. MPC8260 supports multiple DMA implementation methods, which are suitable for different data transmission source/destination devices, different transmission data block sizes and storage modes. Therefore, it is necessary to design a suitable DMA transmission interface according to the system characteristics of the main control board.
1 MPC8260 DMA system structure

diagram 2 CPM principle block diagram
　　MPC8260 is an embedded PowerPC microprocessor designed by Freescale mainly for the data communication field. It has a dual-core structure: a high-performance MPC603e 64-bit RISC microprocessor core and a 32-bit RISC communication processing module (Communication Processor Module, CPM) designed specifically for communication. CPM can share most of the peripheral communication tasks of the PowerPC core, including two DMA controllers, namely serial direct memory access channels (Serial Direct Memory Access, SDMA), so this dual-processor architecture has stronger communication control functions than a single processor. The principle block diagram of CPM is shown in Figure 2. In addition to the PowerPC core and CPM, MPC8260 also includes a flexible system interface unit (System Interface Unit, SIU) mainly used to control the interface with the external bus.
　　In Figure 2, in addition to the SDMA module, CPM also includes a communications controller (Communications Processor, CP), dual-port RAM and some serial peripheral control interfaces. SDMA is connected to the 60x bus and the local bus, and can directly access the dual-port RAM inside the CPM. CP uses these two SDMAs to provide two virtual SDMA channels for each peripheral serial controller: one for input and one for output. At the same time, CPM also uses these two physical SDMA channels to simulate four programmable, independent DMA (Independent DMA, IDMA) channels for data transmission between memory-memory and peripheral-memory.
　　The FPGA and SDRAM on the main control board are both connected to the 60x bus of MPC8260, so IDMA can only be used to achieve DMA transmission between the two. According to the different triggering methods for transmission start, IDMA can be divided into IDMA transmission controlled by handshake signals and IDMA transmission controlled by CP commands. The characteristics of the two methods are introduced below.
1.1 IDMA transmission controlled by handshake signals
　　IDMA transmission controlled by handshake signals is mainly used for data transmission between peripherals and memory. Each IDMA channel has three handshake signals for transmission handshake control: DMA request signal DREQ[1~4], DMA response signal DACK[1~4] and DMA end signal DONE[1~4].
　　In this way, the PowerPC kernel only needs to participate in the initialization of the IDMA channel. The subsequent transmission process is all controlled by the CP according to the channel parameter settings and the handshake signal to control the data transmission and reception, which releases the kernel to the greatest extent. The disadvantages of handshake signal control are: ① The synchronization of data in SDRAM and data in MPC8260 is relatively complicated. ② Bus arbitration is required after each request signal is issued, and after obtaining the right to use the bus, only the size of the peripheral port or 32 bits of data can be transmitted at a time, and the bus utilization rate is low. ③ The handshake control logic and timing are relatively complex, which increases the burden of the internal control logic design of the FPGA.
　　Although this transmission method basically does not occupy core resources, due to the limited bus bandwidth and low utilization, under continuous high-speed communication conditions, the core will not be able to obtain the right to use the bus for a long time and will be in a waiting state. Therefore, IDMA controlled by handshake signals is generally only suitable for transmission initiated by peripherals and data is not too frequent.
1.2 IDMA transmission controlled by CP command
　　The IDMA of MPC8260 can also be internally triggered by writing the START_IDMA command to the CP command register. After each transmission is started, the PowerPC core is released, and the parameters such as the source address, destination address and transmission data length of the transmission are controlled and executed by the CP according to the information initialized in the IDMA channel. The maximum length of each transmission is 4 GB.
　　Compared with IDMA transmission controlled by handshake signals, in this mode, the PowerPC kernel needs to initialize the IDMA channel and start each transmission in the form of a command, so it takes up more kernel resources. However, after a transmission is started, up to 4 GB of data can be transmitted, so as long as the length of each transmitted data is relatively long, the additional overhead of the kernel writing a register can be completely ignored. At the same time, since the internal command trigger method does not require handshake signals and does not need to frequently compete for bus control every few bytes, this method has higher transmission efficiency and faster transmission speed. The internal command trigger method is to exchange space for time - using a large front-end buffer in exchange for an increase in transmission speed.
　　Considering that the bottleneck of the hardware and software systems on the main control board lies in the bus bandwidth, and the storage resources are relatively abundant, the IDMA transmission controlled by the CP command is selected as the transmission method for the data stream from FPGA to SDRAM.
2 DMA transmission scheme design
　　The data transmission interface design between FPGA and MPC8260 is shown in Figure 3. The FPGA on the left side of the figure is connected to the MPC8260 on the right side through a 16-bit data line, a 10-bit address line, 2 interrupt request lines and some read and write control signal lines. MPC8260 is connected to the local memory SDRAM through a 64-bit data line.

Figure 3 IDMA transmission design block diagram
　　Two large storage spaces are allocated inside the FPGA to buffer the data received from the data source in turn. When any buffer is full, the data received is saved to the next buffer, and at the same time, the MPC8260 is triggered by an interrupt to start the corresponding IDMA channel to transfer the data to the SDRAM. IDMA control, data synchronization and error handling are all completed by the MPC8260, and the FPGA is only responsible for sending and receiving data and triggering interrupts. The following introduces the program design of the two respectively.
2.1 MPC8260 Program Design
　　The program processing flow inside MPC8260 is shown in Figure 4. MPC8260 pre-initializes two IDMA channels: the source address of the channel and the length of the transmitted data correspond to the buffer in the FPGA one by one. After receiving the interrupt signal from the FPGA, if the corresponding IDMA channel is idle at this time, a CP command is issued in the interrupt processing program to start receiving data, and the corresponding IDMA channel is set to busy state; otherwise, unread data may be overwritten in the FPGA, and MPC8260 enters the error processing program. At the end of the data transmission, the DMA controller sends a CPM internal interrupt to the kernel. In the interrupt processing program, on the one hand, the parameter settings of the IDMA channel should be restored, and on the other hand, the IDMA channel should be set to idle state to wait for the start of the next transmission. [page]
　　The core part of the MPC8260 program is the IDMA channel setting and interrupt processing.

Figure 4 MPC8260 transmission processing flow
2.1.1 IDMA channel setting
　　Like the general DMA channel setting, the main parameters of the IDMA channel setting include: source address, destination address and transmission data length. In addition, the IDMA channel settings of MPC8260 also include channel mode, buffer and interrupt configuration, etc., involving many registers and complex configuration. The logical structure of the IDMA channel settings is shown in Figure 5.

Figure 5 Block diagram of the logical structure of the IDMA channel settings
　　The BD (Buffer Descriptors) table is a data structure used to specify basic information such as the transmission mode, source/destination address and data length. The base address of the BD table is specified by the value of the IBASE register in the parameter RAM. In addition to the base address of the IDMA BD table, the IDMA parameter RAM also stores IDMA channel information such as the IDMA BD pointer, the starting address of the IDMA transmission buffer, the IDMA transmission buffer size and the DMA channel mode. The base address of the IDMA parameter RAM is specified by the value of the IDMAx_BASE register in the parameter RAM. The address of the IDMAx_BASE register is fixed, such as IDMA1_BASE at the offset RAM base address 0x87FE. The CP initializes the IDMA channel by finding the IDMA parameter RAM through the IDMAx_BASE register and then finding the BD table through IBASE. For specific register configuration, please refer to the IDMA programming example in Chapter 19 of [1].
　　In order to improve the transmission rate of the channel, the following points should be noted when initializing the IDMA channel in the system:
　　① It is necessary to configure the UPM mode for the FPGA in the SIU to control the burst read and write between the MPC8260 and the FPGA. Do not use the General Purpose Chip Select Machine (GPCM) mode. Because the GPCM mode of the MPC8260 memory control does not support burst transmission, when the IDMA works in the GPCM mode, it can only perform ordinary single read and write regardless of whether the length of the transmitted data meets the burst requirement.
　　② Treat the FPGA as a memory, and the IDMA works in the memory-to-memory dual address mode, with the buffer set to a maximum of 2 KB.
　　③ The configuration of the BD table should correspond to the buffer in the FPGA one by one. The CM (Continuous Mode) bit in the BD table structure should be set to the buffer chain mode. After each BD table is transmitted, the valid bit of the BD table is cleared; at the same time, the CP automatically loads the IDMA register according to the value of the next BD table for subsequent transmission. After the
　　IDMA channel is initialized, wait for the CP to issue the START_IDMA command to start transmission. At the end of the last BD table transfer, an interrupt signal is triggered to notify the PowerPC kernel of the completion of this transfer process. The channel setting registers that will change during the transfer process include the IDMA BD table pointer, source address, destination address, and BD table valid bit, so these registers need to be restored in the interrupt handler at the end of the BD table transfer to prepare for the next transfer.
2.1.2 Interrupt processing
　　Two types of interrupt modes are used in the system design: external interrupts introduced by the IRQ pin and internal interrupts triggered by CPM. The initialization process includes: enabling the corresponding interrupt mask bit, selecting the interrupt priority, connecting the corresponding interrupt vector number and the interrupt service program, etc. In order to ensure better transmission real-time performance, the interrupt priority needs to be set as high as possible.
　　The difference from the general interrupt processing process is that the MPC8260 interrupt processing controller uses a hierarchical structure to expand the total number of interrupt signals. The interrupt in the CPM is a secondary interrupt, which needs to be controlled by two levels of interrupts, the CPM interrupt controller and the SIU interrupt controller. The interrupt used to notify the kernel of the end of this transfer process in this design is the BC (BD Completed) signal at the end of the last BD table transfer in the CPM. The BC signal and command end signals send interrupt signals to the kernel through the IDMA bit in the SIU interrupt pending register. Therefore, when the interrupt is initialized, the corresponding bits of the IDMA mask register and the SIU interrupt mask register must be valid at the same time. The specific interrupt initialization example is as follows:
void IDMAint(void) {
　　*(long*)(IDMR1)=0x0F000000;/*Enable all secondary interrupts of IDMA1*/
　　*(long*)(IDMR2)=0x0F000000;/*Enable all secondary interrupts of IDMA2*/
　　*(long*)(SIMR_L)|=0x00000600;/*Enable interrupts of IDMA1 and IDMA2 in SIU*/
　　*(long*)(SIMR_H)|=0x00006000;/*Enable external interrupts IRQ1 and IRQ2*/
　　*(long*)(SIEXR)|=0x00006000; /*Set IRQ1 and IRQ2 to falling edge trigger*/
　　*(long*)(SIUMCR)=0x81210000;/*Configure SIU mode configuration register*/
　　/*Connect interrupt service routine and interrupt vector number*/
　　if((intConnect(INUM_TO_IVEC(INUM_IRQ1),(VOIDFUNCPTR)IRQ1Handler,0))==ERROR)
　　　　logMsg("intConnectIRQ1failedn",0,0,0,0,0,0);
　　if((intConnect(INUM_TO_IVEC(INUM_IRQ2),(VOIDFUNCPTR)IRQ2Handler,0))==ERROR)
　　　　logMsg( "intConnectIRQ2failedn",0,0,0,0,0,0);
　　if((intConnect(INUM_TO_IVEC(INUM_IDMA1),(VOIDFUNCPTR)IDMA11Handler,0))==ERROR)
　　　　logMsg("intConnectIDMA1failedn",0,0,0,0,0,0);
　　if((intConnect(INUM_TO_IVEC(INUM_IDMA2),(VOIDFUNCPTR)IDMA2Handler,0))==ERROR)
　　　　logMsg("intConnectIDMA2failedn",0,0,0,0,0,0);
　　}
　　It should be noted that before the end of the interrupt handling program, the SIU interrupt pending register cannot be cleared directly by writing 1 to the IDMA bit of the SIU interrupt pending register, but by writing 1 to the BC bit of the IDMA event register to indirectly clear the SIU interrupt pending register.
2.2 FPGA Partial Program
　　The FPGA chip in the system uses Xilinx's VirtexII 3000. The large-capacity BlockRAM embedded in VirtexII is configured as a single-port RAM as a buffer. The program can be generated using the IP core built into Xilinx's integrated development environment ISE 7.1i. For FPGA, since the input/output of data is sequential, only one address line is needed at both ends to distinguish between two adjacent data. The address line cooperates with the internal counter to form a read-write pointer. When the write pointer jumps from one half of the buffer to the other half, a corresponding interrupt signal is sent. The
　　key part of FPGA design is the bus interface design with MPC8260. By properly selecting the starting address and length of the buffer, the MPC8260 can read the FPGA in a burst mode. In the design, the burst reading and writing of the MPC8260 to the FPGA follows the UPM mode configured by itself, so the UPM mode design and the FPGA read and write logic design should be considered comprehensively. When designing the UPM mode, the General Purpose Line (GPL) can generate a falling edge to notify the FPGA to write new data to the data bus before the MPC8260 locks the data on the data bus each time; or the bus clock can be sent to the FPGA through the GPL to achieve synchronization of transmission and reception to complete the reading and writing between the MPC8260 and the FPGA.
3 Summary
　　Combining the interrupt processing and IDMA transmission mechanism of the MPC8260, a high-speed data transmission interface between the MPC8260 and the FPGA is designed. The test results show that: the data in the FPGA is copied to the SDRAM in a cyclic read mode, and the data transmission rate is only about 11 Mbps; while the IDMA method introduced in this article can reach a maximum rate of 500 Mbps, and the core occupancy rate is low. The experimental results can fully meet the system design requirements. This study has certain reference value for the interface design of PowerPC series CPU.
References
[1] Freescale. MPC8260 PowerQUICCTM II Family Reference Manual .MPC8260RM Rev.2, 2005-12.
[2] Freescale. MPC8260 PowerQUICCTM II IDMA Functionality.Rev. 3,2006-02.
[3] Freescale. MPC8260 IDMA Timing Diagrams. Rev. 4,2006-07.