Design of multi-window display screen controller based on μC/OS-II

introduction

LED large-screen display screens are the mainstream of outdoor flat display today, and the technology development of their control systems is becoming more and more mature. The control systems are divided into two categories according to the data transmission method: synchronous display and asynchronous display. The synchronous display control system means that the LED display screen and the video data source are kept consistent in real time, and the video signal changes in real time. The asynchronous display control system updates the video data storage area of ​​the large-screen control system through data communication methods such as USB, universal serial interface, and Ethernet. The data update is controlled by the host computer, and the video information change of the LED display screen is determined by the data in the video data storage area. In the asynchronous display system, the display screen can be divided into several areas, and different areas correspond to different storage areas. When the data is updated, only one or several windows can be updated. This design adopts the multi-threaded control method of the embedded operating system μC/OS-II to control the data area of ​​each window separately, realize the display of multiple windows on a single screen at any position, and make the display method more flexible and convenient.

1 Overall design of the system

SOPC technology is used to build Nios II soft core on FPGA as the processor of LED display control system to realize 32-bit embedded system operation. Through the software design of embedded operating system based on μC/OS-II, the reception and preprocessing of DVI video display data are completed. The scanning circuit stores the received video data and reorganizes the data and sends it to the scanning screen.

1.1 System Hardware Structure

The structural block diagram of the multi-window display screen control system is shown in Figure 1.

The computer graphics card data transmits the data to the decoding circuit part of the display control system through the DVI interface. The DVI decoding chip decodes the obtained video data to obtain RGB video data and control signals. The control signal contains a row scan signal and a field scan signal. The display control system determines whether the acquisition of 1 frame of video data is completed based on the field scan signal, and writes the video data into the data storage RAM of the sending system for cache. FPGA reads data from the RAM memory, divides the data into 8 area modules according to the grayscale level, reorganizes and converts the data, and then sends it to the LED display screen for display through the shift serial clock. The data processing module, data storage module, and scanning control module of this system are all implemented on the FPGA.

1.2 Overall software design

The full-color LED large screen has a large amount of data. This design divides the display screen into multiple windows logically, and the software part is implemented based on μC/OS-II embedded operating system programming. The task scheduling algorithm of μC/OS-II operating system is relatively advanced. In the display system, the display operation of each window can be assigned to a task to execute, which can greatly improve the running speed of the entire system and the reliability of the software.

The software is developed based on Nios II IDE, and the application is implemented based on μC/OS-II real-time operating system. The software mainly consists of 2 tasks and 1 timer interrupt service program, and the tasks communicate with each other in the form of semaphores. The graphics card data of the computer system is decoded by the DVI decoding module to obtain RGB video data. Task 1 receives RGB video information and performs processing operations such as filtering, bit combination of data, and recombination of data storage areas on the video information. Task 2 reads data from the memory, analyzes and processes it, and sends the analyzed and processed data to the scanning control module. Taking advantage of the real-time and multi-tasking characteristics of μC/OS-II, an embedded file system is used for data management.

2 Design plan for the hardware part of the controller
2.1 Analysis of the video data decoding module

The data is obtained from the DVI interface of the graphics card, and the video control system performs appropriate data conversion before sending it to the LED display screen for display. This module is used to obtain video source data and complete the reception of TMDS encoded data transmitted by the DVI interface of the graphics card. Through TMDS decoding, the RGB video data and the pixel clock CLOCK, pixel valid signal DE, line synchronization signal HSYN, field synchronization signal VSYN, synchronization detection signal SCDT and other video display control signals are restored.

The DVI differential signal output by the computer graphics card cannot be directly used as the scanning data signal of the LED. It needs to be decoded to restore the signal to digital video data RED[7. 0], GREEN[7. 0], BLUE[7. 0] and other pixel information. It is also necessary to restore control signals such as line synchronization signal HSYNC, field synchronization signal VSYNC, data enable signal DE and clock CLK and other control information
. A decoding circuit is needed to decode the DVI differential signal. This design uses the TFP401A DVI decoding chip to implement this function. The decoded data information is used to provide to the LED screen controller.

2.2 Analysis of data storage organization modules

There are two ways to organize data written into SRAM memory: bit plane method and combined pixel method. The bit plane method means that each bit of the pixel is stored in different storage devices; the combined pixel method means that all bits of each pixel on the screen are stored in a single storage device. The weight of each bit of the LED screen pixel data is different. The high weight is high, which means that the LED will be lit for a longer time when the high bit is 1. According to the characteristics of the two storage structures, for LED screens, the use of bit plane structure is conducive to improving the display effect of LED screens, making it easier to achieve D/T (data to time) conversion. The data of the bit plane method needs to be reorganized, and the use of bit plane structure is conducive to improving the display effect of LED screens. The schematic diagram of data reconstruction is shown in Figure 2.

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After data reconstruction, the QuartusⅡ software is used to compile the simulation waveform shown in Figure 3. When col is 1, it means that the data of the above 8 addresses have been written, and the read address counter starts counting. datain is the serial input data, and dout is the serial output data.

2.3 Scanning Control Module

The digital video signal is cached and processed, and the RGB signal is converted into the signal required for LED display through pulse width modulation (PWM) and sent to the scanning module. The scanning control module consists of a user-defined PWM IP core and video memory. The video memory is implemented with a piece of SRAM to save the dot matrix information data of the current display. The PWM module is connected to the Nios II CPU through the Avalon bus, writes the data received from the CPU into the video memory according to the specified address, and then reads the dot matrix information data from the video memory according to a certain addressing method for scanning.

2.4 Other functional modules

The serial port controller, timer, and memory controller are automatically generated through the custom integrated IP core of SOPC Builder software.

3. Design of control system software

The operating system schedules each task using an efficient task scheduling algorithm, and the display of each window is completed by a single task.

3.1 Data Structure

The storage format of data in the memory directly affects the data access speed and control complexity. This system reorganizes the data in the video memory and the data in the cache area, reducing the complexity of data processing and scanning control.

3.1.1 Video Memory Data Organization

Each pixel of the LED display screen includes three primary colors: red, green, and blue. The grayscale of each color is 256 levels, that is, the grayscale of the pixel is encoded by 8-bit data, so each pixel needs to occupy 3 bytes of storage space. When displaying, the red tube, green tube, and blue tube of each pixel are lit at the same time, that is, the data of the three colors are displayed on the screen in parallel. Based on this, the data corresponding to the three colors of red, green, and blue can be stored separately for easy operation. The data storage method is shown in Figure 4. The data of each color is stored in a certain area, and the first address of each area is used as the base address of the three colors. When storing data, each pixel only needs to give a relative change address (addressing), and then add different base addresses to find the video data of the corresponding point in the three areas.

The implementation method of grayscale of LED display screen is weighted scanning. In this way, the color data bits need to be separated, and then the bits with the same weight are recombined. For the convenience of operation, each area in the partition shown in Figure 4 is divided into 8 weight areas during storage, and all values ​​with the same weight are concentrated in the corresponding weight area. The so-called bit separation is to separate the high and low bits of the data according to the weight and then reorganize it. The implementation of bit separation is also relatively easy to implement in programmable logic devices. A logic matrix can be drawn out, and it can be stored horizontally and read vertically during operation. The schematic diagram of bit separation is shown in Figure 5.

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3.1.2 Organization of cached data

If special effects are to be displayed, there is a certain transformation relationship between the currently displayed data frame and the next data frame. Since the CPU can only write to the video memory, it is necessary to divide a screen area in the cache that is equal in size to the video memory and has a one-to-one corresponding address to store the currently displayed data frame information. If there is overlap between windows, and the special effects data processing operation is performed directly in the screen area, the information of the overlapping parts of the windows may be confused. Therefore, an access space (part 1, part 2, ..., part n) is divided for each window in the cache to store the previous frame of data information displayed in this window. During the special effects data processing operation, the data information of each window is first processed in the part area, and then the converted data is sent to the access space of the address corresponding to each window in the screen area. Finally, the data in the screen is written to the video memory corresponding to the address, thereby completing the display.

3.2 Software Design

Based on the above scheme, the design of the program will become very simple. First, the system is initialized, and then the screen parameters are read from Flash to initialize the parameters. Then the task Task Control is established to manage the window display tasks in real time. It has a higher priority than the window display tasks. It queries the reset flag once every 1 second. If reset=1, it deletes the previously established window display tasks, reads the new number of windows from Flash, and then establishes a new task accordingly, and the display of each window is controlled by a single task.
The following is a program demonstration of the TaskControl task:


The window display task is used to realize the display of each window on the screen. It can perform the calculation of the next frame of data in the corresponding area according to the different display modes of each window. After completing the display of 1 frame of data, OSTime DlyHMSM() is called to put the current task into the waiting state and perform a task scheduling, handing over the system control to other display tasks in the ready state, thereby completing the switch between the window display task and the window display task. You can also change the time interval between two frames of information displayed in each window by adjusting the parameters of OSTimeDlyHMSM(), so as to adjust the special effects of each window, such as the moving speed of the moving display. The following is a program demonstration of one of the window display tasks:


4 Conclusion

This design makes full use of the high performance of the Nios II 32-bit processor and the efficient task scheduling algorithm of the μC/OS-II real-time operating system to achieve single-screen multi-window display, making the display control more flexible. The entire control system is completed on a single FPGA chip, effectively reducing the cost of the system.