Wiring resources connect all units inside the FPGA, and the length and process of the connection determine the driving ability and transmission speed of the signal on the connection. There are abundant wiring resources inside the FPGA chip, which are divided into 4 different categories according to the process, length, width and distribution location. The first category is global wiring resources, which are used for the wiring of global clocks and global reset/sets inside the chip; the second category is long-line resources, which are used to complete the wiring of high-speed signals and the second global clock signal between chip banks; the third category is short-line resources, which are used to complete the logical interconnection and wiring between basic logic units; the fourth category is distributed wiring resources, which are used for proprietary clock, reset and other control signal lines.
In practice, designers do not need to directly select routing resources. The layout and routing tool can automatically select routing resources to connect various module units based on the topological structure and constraints of the input logic netlist. In essence, the use of routing resources is closely and directly related to the design results.
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