Innoda releases RTL-level power consumption analysis tool to promote energy-efficient IC design

(Abstract: Innoda has released the independently developed EnFortius® RTL-level power consumption analysis tool, which can optimize circuit design early in the IC design process.)

(November 1, 2023, Chengdu, Sichuan) Innoda (Chengdu) Electronic Technology Co., Ltd. released the EnFortius® RTL-level power analysis tool (RPA) to evaluate circuit power consumption in the early stage of IC design , optimize the circuit design early. This tool is the third tool in Innoda's low-power EDA series. From low-power static check (LPC) to gate-level power analysis (GPA), Innoda continues to move forward with this latest tool. Advance and explore the road to power consumption optimization.

In the entire chip design process, it is crucial for the design team to continuously track and obtain accurate power consumption data. This not only means that the power consumption level changes at various abstract stages (RTL level, gate level) and levels (SoC level, Block level) is transparent and controllable, driving the design team to make better design decisions ; in addition, through continuous management and optimization of power consumption, it can also improve design efficiency and save iteration costs caused by power consumption.

Especially in the early stages of the IC design stage (RTL stage), accurate and consistent evaluation and analysis of power consumption is required to provide modification suggestions for the chip design. The effect of power consumption design optimization is best at this stage because of the abstraction level at this stage. High, the flexibility of modification is also higher, and the later it is, the smaller the space for optimization is. Therefore, it is necessary to repeatedly perform power consumption estimation during the RTL stage and conduct power consumption comparisons for different design architectures to ultimately evaluate and improve the energy efficiency of the design.

In this process, due to the lack of logical synthesis and the lack of important data such as physical information, it is very difficult to accurately estimate power consumption. Design teams need simulation data, process library files, and other reference data to get closer to real power consumption. So design teams need an advanced set of tools and design processes to obtain accurate power consumption data at an early stage.

Innoda's EnFortius® RPA is a static analysis tool used to estimate IC power consumption in the RTL stage . It can help users obtain accurate power consumption data in the early stages of design, find power consumption hot spots in the design, optimize power management strategies, and thereby reduce circuit costs. power consumption. This tool supports industry standard input files, and also uses Innoda's independently developed efficient and fast logic synthesis engine and physical line network model to further improve the accuracy of power consumption estimation.

Features and Benefits of EnFortius® RPA

• Integrated power consumption solutions can conduct comprehensive analysis of power consumption at different design abstraction levels (RTL level, gate level, SoC level and Block level);

• Supports industry standard input files:

•  System Verilog;

• Liberty files that provide process library unit data;

• SAIF/FSDB files that provide signal activity information;

• SPEF file providing parasitic parameter information;

• Self-developed efficient logic synthesis, gate synthesis and clock tree synthesis engines; 

• The self-developed and patented physical line network model can complete more accurate line network capacitance estimation through the existing physical data of the reference design;

• Fast signal probability and signal flip rate propagation algorithm;

•  Perform peak power and peak activity analysis;

• Supports multi-voltage domain power consumption analysis with different voltages;

• Analysis and reporting of various indicators, such as dynamic and static power consumption of each logic level and logic group, clock gating ratio (CGR) and clock gating efficiency (CGE), etc.;

• Innovative and efficient data and algorithm architecture can complete power consumption analysis of ultra-large-scale designs (equivalent to over 100 million logic gates);

• A new paradigm for power consumption estimation and exploration in RTL stage

Based on independent innovation, Innoda's product not only fills the gap in the domestic EDA market , but also innovatively explores the power consumption estimation and analysis process. It has obtained a number of invention patents.

“The RTL-level power consumption analysis tool released this time adopts the latest software development technology and has made innovations in both data and algorithm architecture. It can help design projects of very large-scale integrated circuits such as SoC to quickly complete accurate and consistent functions. Consumption assessment and analysis." Dr. Wang Qi, founder and CEO of Innoda, said, "As an indispensable part of the current mainstream design process, I believe this tool will become a reliable and effective tool for customers in the process of power consumption optimization. Assistant. In the field of low-power design, Innoda will continue to leverage its advantages, continue to explore ways to optimize power consumption, and provide better tools for the industry.”

Jiang Jiang, President of Super Rui Technology, said: "The scale of IC design is getting larger and larger, and the power consumption density continues to increase, which has become a barrier to the development of high-performance chips. Based on its previous gate-level power consumption analysis tool, Innoda's This RTL-level analysis tool is fast and can accurately predict the power consumption of large-scale circuits at the RTL stage. I am very happy to see another innovative breakthrough of domestic EDA, and I look forward to Innoda continuing to work hard to design EDA tools with low power consumption. The field continues to expand, from power consumption inspection to power consumption analysis, from RTL to Signoff to provide the industry with more complete and comprehensive low-power solutions.”

Wang Fang, verification manager of Xiongli Technology, said: "Power consumption is one of the bottlenecks faced by the design team. Innoda's RTL-level power consumption analysis tool can help engineers accurately estimate static and dynamic power consumption in the early stage of chip design. By exploring different The code power consumption comparison quickly converges and realizes power consumption optimization in the early stage of design. Combined with Innoda’s other low-power solutions, I believe that the design team can complete low-power designs more efficiently and help us launch more competitive products. IC products.”

On November 10-11, Innoda will appear at ICCAD 2023 in Guangzhou, where Innoda's comprehensive low-power solutions will be introduced and demonstrated to the audience. On the afternoon of November 11th at the [EDA and IC Design Special Forum], Innoda will share relevant technologies. At the same time, we sincerely invite you to visit our booth for guidance.