Synopsys launches ZeBu Server 5, the industry’s first high-performance simulation system, to help realize system-level chip electronic digital twins

Synopsys' ZeBu Server 5 hardware emulation system has a sales capacity of over 400 billion doors in its first year, accelerating the design of complex SoC and multi-die chip systems

Summary:

• Electronic digital twins enable dynamic digital representation of electronic systems to accelerate software launch, power consumption analysis and SW/HW verification

• Synopsys ZeBu Server 5 provides a capacity of up to 30 billion gates, with twice the throughput and energy efficiency compared to the previous generation.

Mountain View, Calif., May 26, 2023 – Synopsys, Inc., recently launched the Synopsys ZeBu® Server 5 hardware emulation system to handle complex billion-gate and multi-die chips System challenges in software startup, power consumption optimization and debugging . Compared with the previous generation product, the capacity of Synopsys ZeBu Server 5 has been expanded by 1.6 times, the throughput and simulation performance have been increased by 2 times, while the power consumption is less than half.

Ravi Subramanian, general manager of Synopsys' System Design Division, said: "Currently, reproducing complex scenes in the physical world or metaverse in software-driven systems such as advanced automobiles or VR headsets requires powerful computing power to support The operation of cutting-edge algorithms. Making these products good means that the software running on the chip must be fully tested through a hardware simulation system for tens of billions of clock cycles before being put into production. The performance of Synopsys ZeBu Server 5 hardware simulation system is far ahead in the industry. , has successfully provided customers around the world with a capacity of more than 400 billion gates, becoming one of the most successful hardware emulation products in the industry."

ZeBu Server 5, a new addition to Synopsys' industry-leading hardware-assisted verification portfolio, is now generally available.

Software and hardware collaborative optimization contributes to system success

Faced with verification workloads in billion-gate designs and multi-die systems, performance, capacity and reliability are key to accelerating software launch and hardware development. Digital twins play an important role throughout the product lifecycle, providing a digital copy of an electronic system for software launch, power consumption analysis, and SW/HW verification. Semiconductor and system-level companies can collaborate more closely through digital twins to ensure development works as expected and avoid costly chip re-creations. New features in Synopsys ZeBu Server 5 enhance electronic digital twin capabilities and help developers accelerate the development of production-ready chips. In addition, the system also supports cloud access, so developers can flexibly adjust the system scale and carry out verification work according to project needs.

Alex Starr, AMD Corporate Fellow, said: “While multi-die system designs help systems cope with the overwhelming demands of compute-intensive applications, bringing these complex systems to market quickly is a serious challenge. New The designed Synopsys ZeBu Server 5 is perfectly adapted to the AMD Virtex UltraScale+VU19P FPGA, enabling rapid simulation under current stringent design capacity requirements, helping our most challenging designs meet stringent market requirements.”

Hyundon Kim, principal engineer at Samsung, said: "For the billion-gate-level designs required for today's computing-intensive applications, only electronic digital twins can improve and accelerate the debugging process. With high capacity and high throughput, Synopsys ZeBu Server 5 provides Samsung’s Exynos SoC products provide an ideal pre-silicon verification solution, helping us achieve software launch and hardware development in advance.”