TSMC releases more 3nm details, expects mass production in 2022

At TSMC's annual technology seminar, the characteristics of the future 3nm process node were introduced in detail, and a roadmap was planned for subsequent 5nm products, including the N5P and N4 process nodes.

Starting with TSMC's upcoming N5 process node, which represents the second generation of deep ultraviolet (DUV) and extreme ultraviolet (EUV) nodes after the rarely used N7+ node (used by the Kirin 990 SoC, for example). TSMC has already started volume production for a few months, and Apple's next-generation SoCs may be the first candidates for this node.

TSMC detailed that N5's current defect density is one-quarter better than N7, and the new node has a higher yield in mass production than its predecessor major nodes N7 and N10, and defect density is expected to continue to improve, exceeding the historical trend of the past two generations.

The foundry is also preparing a new N5P node, based on the current N5 process, that promises a 5% speed increase and 10% reduction in power consumption.

In addition to N5P, TSMC is also introducing the N4 node, which represents a further evolution of the N5 process, with more EUV layers to reduce masks, with minimal migration work required for chip designers. We will see N4 risk production start in Q4 2021, with volume production later in 2022.

The biggest news today is that TSMC disclosed their next-generation N5 process node family, the 3nm process N3. They started defining this node last year and are currently progressing smoothly.

Contrary to Samsung's 3nm process node's use of the GAA (Gate all around) transistor structure, TSMC will stick with FinFET transistors and rely on "innovative features" to achieve the full-node expansion promised by N3.

PPA improvement with new process technology

Compared to the N5 node, N3 promises to improve performance by 10-15% at the same power level, or reduce power by 25-30% at the same transistor speed. In addition, TSMC promises a 1.7x increase in logic area density. Of course, this shrinkage does not directly target all structures, the density of SRAM is only improved by 20%, and the analog structure will improve even less.

Modern chip designs are very SRAM-heavy, with a typical SRAM/logic split of 70/30, so at the chip level, the expected shrink is only 26% or less.

N3 is scheduled to enter risk production in 2021 and volume production in the second half of 2022. The process characteristics disclosed by TSMC on N3 will not differ much from the power and performance disclosed by Samsung on 3GAE, but will lead more in density.