Implementation of Synchronous Ethernet Based on IEEE 1588

1 Background

IP is the development trend of future network services, and Ethernet has become the main development direction of IP-based bearer networks with its superior cost-effectiveness, wide application and product support. When deploying carrier-grade Ethernet, how to solve the clock synchronization problem is an aspect to be considered. There are two aspects of the synchronization requirements for packet networks: first, the packet network can carry TDM services and provide a mechanism for TDM service clock recovery so that TDM services can still meet certain performance indicators after traversing the packet network; second, the packet network can provide a high-precision network reference clock like the TDM network to meet the synchronization requirements of network nodes or terminals.

Synchronous Ethernet (SyncE) is the latest standard solution. In SyncE, Ethernet synchronizes its bit clocks through a high-quality, traceable primary reference clock signal in the same way as SONET (Synchronous Optical Network)/SDH (Synchronous Digital Hierarchy). In 2006, the International Telecommunication Union described the SyncE concept in its G.8261. In 2007, the performance requirements of SyncE were standardized in G.8262, which specifies the minimum performance requirements for clocks used in synchronous Ethernet network equipment. In 2002, the IEEE released the IEEE 1588 standard, which defines a precision time synchronization protocol (PTP), and in 2005, a new version of IEEE 1588, namely IEEE 1588v2, was developed.

2 Related standards and protocols

2.1 IEEE 1588

IEEE 1588 achieves more accurate timing synchronization through the coordination of hardware and software. No additional clock line is required when transmitting time clock signals, and the original Ethernet data line is still used to transmit the clock signal, which simplifies the network connection and reduces costs.

IEEE 1588 specifically defines a message-based synchronization protocol in its technical specifications. By periodically publishing information packets with timestamps, the clocks of each measurement and control node can be corrected, thereby achieving synchronous operation of the entire system. The implementation principle is shown in Figure 1.

Figure 1 Clock error correction principle

First, the master clock node periodically (usually every 2 seconds) sends a synchronization packet (Sync) to the entire system, then packs the synchronization packet timestamp and sends a synchronization follow-up packet (Follow Up). When each slave clock node receives the synchronization packet and synchronization follow-up packet sent by the master clock node, it calculates the master-slave clock difference based on its own timestamp, the received synchronization packet timestamp, and the parsed synchronization follow-up packet timestamp; and uses this difference to adjust its own clock until it is synchronized with the master clock.

In a distributed measurement and control system, the location of each measurement and control device in the network, the wiring method, the wiring length, and the inherent problems in the current network technology will also cause different delays in the transmission of measurement and control data. In order to effectively eliminate the impact of network delay on the real-time performance of distributed systems, IEEE 1588 also defines two information packages. The correction principle is shown in Figure 2.

Figure 2 Network delay correction principle

The slave clock node can send a delay request packet (Delay Request) to the master clock node irregularly (usually 4 to 60 seconds). After receiving the delay request packet, the master clock node immediately packages the receiving timestamp and returns a delay response packet. When the slave clock node receives the delay response packet, it calculates the network delay time based on the timestamp of the delay request packet it sends and the timestamp of the parsed delay response packet, and uses this difference to adjust its own clock until it is synchronized with the master clock. Based on the above method, the master-slave clock difference and the transmission delay of the measurement and control data in the network can be effectively eliminated, thereby realizing the clock synchronization of the distributed networked measurement and control system.

2.2 Distribution of reference clock signal

G. 8261 defines the timing synchronization network elements in the packet network, specifies the maximum jitter and drift values ​​allowed in the network, and the minimum jitter and drift tolerances that need to be achieved when the packet network boundary and TDM interface are connected; summarizes the minimum requirements for network elements to achieve synchronization functions; proposes two methods of allocating reference clock signals - network synchronization method (synchronous Ethernet) and packet-based method, which solves the synchronization problem of packet networks, especially Ethernet. It is particularly pointed out that the two allocation methods have their own advantages, and their mixed application will build a next-generation synchronization network that can achieve both frequency synchronization and time synchronization.

(1) Network synchronization method (synchronous Ethernet)

Like the current SONET/SDH link, synchronous Ethernet achieves network synchronization through the first layer (i.e., physical layer) of the OSI seven-layer protocol. The synchronous Ethernet method is also called the "PRC distribution method" (such as GPS) or the master-slave method of the synchronous physical layer. It supports clock distribution based on the network synchronous line code method and has been widely used in synchronous TMD networks.

Its characteristics are: using the Ethernet physical layer; only being able to allocate synchronization frequency but not synchronization time; not being affected by damage to the upper layers of the network; good synchronization quality and high reliability.

(2) Based on grouping

This method means that the timing information is carried by packets, and a special timestamp message is sent. The method for bidirectionally transmitting timing information may be NTP or a similar protocol. It is worth noting that the bidirectional protocol can also transmit time information.

Its characteristics are: it is independent of the physical layer; it can allocate synchronization frequency and synchronization time; it will be affected by damage to the telecommunications network, such as packet delay jitter.

3 Application Examples

3.1 Si5315 chip

In actual applications, the Si5315 chip produced by Silicon Labs is used. This chip is a jitter attenuation clock multiplier chip that uses a dual clock input of 8 kHz to 644.53 MHz and generates two independent multiplied clocks. In terms of synchronization, Silicon Labs' third-generation DSPLL technology is mainly used, which can generate frequency synthesis at any ratio and de-jitter at high rates. In addition to supporting SONET/SDH and Ethernet clocks, Si5315 can also support synchronous Ethernet clock multipliers with 10G line coding rates.

A specific application example is shown in Figure 3. The local clock input is 62.5 MHz as one input of the chip, and after being multiplied by Si5315, the output port is 125 MHz. Its signal is introduced into the CDR module (data clock recovery module) of the Ethernet device as a reference clock. When the data enters the CDR, a clock close to 62.5 MHz is recovered and input into Si5315 again. After the DPLL phase lock reaches the clock that the chip considers to meet the requirements, the input of the local clock is shielded. When all devices in the network complete this operation, the clock synchronization of the entire network is completed. In specific applications, the data clock of the previous stage often has severe jitter. After being processed by the Si5315 chip, the clock can be recovered very well, and the clocks of all devices remain consistent.

Figure 3 Si5315 synchronous chip application example

3.2 DP83640 chip

IEEE 1588's Precision Time Protocol (PTP) can achieve high-precision Ethernet time synchronization, but if you need to achieve ns-level clock synchronization performance, it is difficult to achieve it only through software. This is because after receiving PTP packets on the line, each device that processes them will increase the synchronization error. DP83640 makes ns-level clock synchronization possible through hardware plus software at the physical layer.

DP83640 is a clock synchronization chip based on IEEE 1588 standard. It uses hardware and software to provide the highest precision real-time industrial clock synchronization, ensuring that each node in the distributed system can synchronize the time according to the host clock and that the time deviation between nodes does not exceed 8 ns. Once there is a PTP packet on the line, it will be read by the precision PHYTER of DP83640.

DP83640 has several internal clocks, including a local reference clock, an Ethernet receive clock, and a PTP clock signal source; it also includes an internal PTP digital counter and logic that can control the digital counter and PTP clock rate (frequency).

In the solution of synchronous Ethernet switch, it is realized by replacing the Ethernet layer and adding IEEE 1588 PTP software. As shown in Figure 4, the CPU, switch chip and DP83640 are connected through the MII port to form a system. The switch becomes a synchronous device in the Ethernet, so that the Ethernet formed by the switch and the devices attached to the network meet the IEEE 1588 protocol, and finally form a synchronous Ethernet.

Figure 4 Application block diagram of synchronous Ethernet switch based on DP83640

Conclusion

From the current prototype experiments and applications, the precise time protocol standardized in IEEE 1588 can achieve sub-microsecond synchronization accuracy, and may achieve higher accuracy. IEEE 1588 provides an effective solution for real-time applications of standard Ethernet based on multicast technology, but there are also some issues that need further study, such as the fault tolerance of the master clock and the impact of the oscillator's stability on the clock. I believe that the standard will be more perfect in the future, and there will be more specific applications to refer to.