Data transmission modulator/demodulator circuit diagram composed of SST8803 and UM3758-108A

The main component ICl of this circuit is the new power grid carrier digital pulse signal transmission modulation /demodulation integrated circuit SST8803. It has the characteristics of low power consumption, high sensitivity, good anti-interference and anti-static performance, and can complete the modulation of data signals with a single chip. All work of transmit and receive demodulation. It can use low-voltage power lines, broadcast lines and closed-circuit television signal lines as carriers for data information exchange, and can be used in systems such as remote control telemetry, centralized alarm, multi-channel paging and microcomputer networks.

Figure (a) shows the typical application circuit of SST8803. Pins ⑩ and ⑥ of ICl are the positive and negative power supply terminals. The minimum applied voltage limit is -0.3V and the maximum is 6.5V. Pin ⑧ is the reference voltage output terminal, VREF=VDD/2, pin ⑨ is externally connected to C11 as a filter capacitor. The internal circuit of pins 11 and 12 and the quartz crystal X1 generate a 455kHz clock signal, which is used for signal modulation or demodulation. Pin 15 is the working mode selection terminal. When the level is raised low, it is in the modulating and transmitting state. When the level is raised high, it is in the receiving and demodulating state. It can easily realize half-duplex communication. R7, C7, and VD2 form an automatic reset circuit. VDl is a 6.5V voltage-limiting protection tube, which ensures that the circuit is not damaged when the power grid generates transient pulse high voltage.

Figure (b) is an example of matching SST8803 with a digital encoder/decoder. IC2 is a digital signal encoding and decoding compatible device UM3758-108A. Its clock frequency is f=l/0.5Rs·Cs. This circuit takes f=160kHz. Pins ①~⑩ of IC2 are three-state address code input terminals, and the maximum address code capacity is 310=59049. IC211~18 pins are data input (when encoding)/output (when decoding) terminals. This is an 8-bit parallel port. Sl is the working mode selection switch. When encoding, pin 21 of IC2 is high level. After being inverted by the inverter IC3-1 of CD4069, pin 15 of ICl is low level (modulation state). The encoded data stream is serialized by pin 23 of IC2. Line output to ICl pin 5, modulated and sent to the power grid; during decoding, IC2 pin 21 is low level, IC1 pin 15 is high level (demodulation state), and the demodulated digital signal is sent to IC1 pin 17 IC2 pin 22, after decoding, it is output by IC2 pins 11~18. At this time IC2. The pin is connected to the light-emitting diode LEDl. If the input signal is valid, IC2 pin 23 outputs a low-level signal and drives LEDl to flash once as a sign of successful reception and decoding.