What guarantees the stable operation of smart substations?

The secondary system of a smart substation usually includes electronic transformers, merging units, switches, protection and measurement and control equipment. These devices must operate based on a unified time reference, which places strict requirements on the clock synchronization system of the smart substation. How is the microsecond-level time synchronization system of the smart substation achieved?

Time is a basic physical quantity, so time also has accuracy issues. Different time sources have different accuracy. For example, when Apple Watch is used with iPhone, the error with UTC time does not exceed 50ms. The 50ms error can be ignored for human perception, but it is unsatisfactory if used in smart substations.

The secondary system of a smart substation usually includes electronic transformers, merging units, switches, protection and measurement and control equipment. These devices must be operated based on a unified time reference to meet the requirements of event sequence recording (SOE), fault recording, and real-time data acquisition time consistency, and ensure the accuracy of line fault distance measurement, dynamic monitoring of phase and attack angle, and unit and power grid parameter verification. These requirements place strict demands on the clock synchronization system of the smart substation.

The IEC61850 standard divides substations into the station space layer, the bay layer, and the process layer. The requirements for time synchronization accuracy are different for each layer of equipment. Bay layer equipment needs to reach ms accuracy; while process layer equipment, because it mainly transmits sampling values ​​and tripping information, needs to achieve μs synchronization accuracy. The DT6000 series (DT6000, DT6000E and DT6000S) of smart substation test equipment can achieve μs synchronization accuracy, which fully meets the time synchronization accuracy of equipment at each layer of the substation.

DT6000 Series Timing System
 

Figure 1.1 DT6000 series time synchronization

The DT6000 series supports IRIG-B, PPS and IEEE1588, as shown in Figure 1.1. All three protocols use FPGA hard decoding, which is converted into UTC time stamp after decoding, and provides time to other protocols such as SMV and GOOSE. For example, the received time stamp of SMV and GOOSE is a hard time stamp, which is marked by FPGA, and the time information is inserted into the message, and the message information and time are saved in real time. While synchronizing the time, FPGA also performs time calibration, that is, correcting the error (μs level) caused by the local crystal oscillator, and dynamically adjusting the uniform adjustment error value.

1.1.1 Time Synchronization

  1. PPS time synchronization

There are two important criteria for determining whether PPS is normal or not:

(1) The time interval between the rising edges of adjacent pulses is 1s. When the time interval between the rising edges of adjacent pulses differs from the ideal time interval (1s) by more than 10μs, the input is considered abnormal.

(2) Pulse width is greater than 10μs, and pulse interval is greater than 500ms. When the measured pulse width is less than 10μs, or the measured pulse interval is less than 500ms, the input is considered abnormal.

The DT6000 series filters the input signal based on the above two criteria to remove the burr signal. As shown in Figure 1.2, after the DT6000E is synchronized with the PPS, the SMV sampling counter is reset to zero at the whole second.

Figure 1.2 SMV sampling counter cleared in full second

2. IRIG-B timing

The frame period of IRIG-B code is 1s, containing 100 code elements, and each code element period is 10 ms, that is, the code element rate of IRIG-B code is 100pps. IRIG-B code has 3 code elements, binary "0", "1" and position identification mark Px, with pulse widths of 2ms, 5ms and 8ms respectively. The pulse signal is shown in Figure 1.3.
 

Figure 1.3 IRIG-B code element diagram

Two consecutive "P" symbols indicate the beginning of a whole second. The pulse leading edge of the second "P" symbol is the "punctual" reference point, which is defined as "Pr", followed by information related to the current time and time control. The "punctual" reference point of the whole second of IRIG-B requires the SMV sampling counter to be cleared, which is the same as PPS, as shown in Figure 1.2.
Figure 1.4 shows the IRIG-B time synchronization of DT6000E.
 

Figure 1.4 IRIG-B timing

3. IEEE1588 time synchronization

The decoding and time stamping of IEEE1588 messages are both performed in FPGA, working in Slave mode. Time stamping refers to the process of marking the synchronization message with local clock information when the synchronization message enters or leaves the protocol stack. The method of obtaining the timestamp directly affects the accuracy of clock synchronization. The closer the location of obtaining the timestamp is to the physical layer, the better it can avoid the delay jitter of the message in the protocol stack, and the higher the synchronization accuracy that can be achieved. Decoding and time stamping messages in FPGA is time stamping at the MII layer, which is hardware time stamping and has the highest accuracy.
Figure 1.5 shows the IEEE 1588 time synchronization of DT6000E.
 

Figure 1.5 IEEE 1588 time synchronization

1.1.2 Time calibration

The DT6000 series will also perform time calibration while synchronizing the time to correct the error value of the local crystal oscillator. Figure 1.6 is an example of time calibration adjustment. It can be seen from the figure that the first rough adjustment value is +99, the second precise adjustment is positive, and the Value at this time is +99+9=+108, and the third precise adjustment is reverse, and the Value at this time is +108-2=+106. While obtaining the Value value, the counter is also being adjusted evenly.

Figure 1.6 Time calibration example diagram

The time calibration circuit (FPGA) operates at a main frequency of 100MHz. After actual measurement and calibration, the accuracy error does not exceed 20 cycles (10ns) in an environment with little temperature change. After calibration, the time accuracy can be changed from μs level to 200ns level. And after using the time calibration circuit, the high accuracy of the local time can be maintained for a long time after the time calibration device is removed.

1.1.3 Timing

The DT6000 series supports IRIG-B code and PPS timing. The DT6000S has two optical serial ports, so it supports simultaneous timing of two optical serial ports. Figure 1.7 shows the IRIG-B code timing interface of the DT6000E, which is equivalent to the PPS timing.

Figure 1.7 IRIG-B code timing