Considerations on Power Signal Integrity in PCB Design

　　In circuit design, we are generally concerned about the quality of signals, but sometimes we tend to limit our research to signal lines and treat power and ground as ideal situations. Although this can simplify the problem, this simplification is no longer feasible in high-speed design. Although the more direct result of circuit design is reflected in signal integrity, we must not ignore the power integrity design. Because power integrity directly affects the signal integrity of the final PCB board. Power integrity and signal integrity are closely related, and in many cases, the main reason affecting signal distortion is the power system. For example, the ground bounce noise is too large, the design of decoupling capacitors is not appropriate, the loop impact is very serious, the division of multiple power/ground planes is not good, the formation design is unreasonable, the current is uneven, etc.

　　1) Decoupling capacitors

　　We all know that adding some capacitors between the power supply and the ground can reduce the noise of the system, but how many capacitors should be added to the circuit board? What is the appropriate value of each capacitor? Where is the best place to put each capacitor? We generally don't seriously consider these questions, but just rely on the designer's experience, and sometimes even think that the fewer capacitors, the better. In high-speed design, we must consider the parasitic parameters of the capacitor, quantitatively calculate the number of decoupling capacitors, the capacitance of each capacitor, and the specific location of placement to ensure that the impedance of the system is within the control range. A basic principle is that all the required decoupling capacitors must be included, and no extra capacitors should be included.

　　2) Ground rebound

　　When the edge rate of high-speed devices is less than 0.5ns, the data exchange rate from the large-capacity data bus is particularly fast. When it generates strong ripples in the power layer that are strong enough to affect the signal, power instability problems will occur. When the current through the ground loop changes, a voltage is generated due to the loop inductance. When the rising edge is shortened, the current change rate increases, and the ground bounce voltage increases. At this time, the ground plane (ground wire) is no longer an ideal zero level, and the power supply is not an ideal DC potential. When the number of gate circuits switched at the same time increases, the ground bounce becomes more serious. For a 128-bit bus, there may be 50_100 I/O lines switching on the same clock edge. At this time, the inductance of the power and ground loops fed back to the I/O drivers that switch at the same time must be as low as possible, otherwise, a voltage brush will appear when connected to the same ground. Ground bounce can be seen everywhere, such as on chips, packages, connectors or circuit boards, which may cause power integrity problems.

　　From the perspective of technological development, the rising edge of devices will only decrease and the width of buses will only increase. The only way to keep ground bounce acceptable is to reduce the distributed inductance of power and ground. For chips, it means moving to an array wafer, placing as much power and ground as possible, and making the connection to the package as short as possible to reduce inductance. For packages, it means moving the layer package to make the spacing of the power and ground planes closer, such as used in BGA packages. For connectors, it means using more ground pins or redesigning the connector to have internal power and ground planes, such as connector-based ribbon cables. For circuit boards, it means making adjacent power and ground planes as close as possible. Since inductance is proportional to length, making the power and ground connections as short as possible will reduce ground noise.

　　3) Power distribution system

　　Power integrity design is a very complex matter, but how to control the impedance between the power system (power and ground plane) is the key to the design. Theoretically, the lower the impedance between the power systems, the better. The lower the impedance, the smaller the noise amplitude and the smaller the voltage loss. In actual design, we can determine the target impedance we want to achieve by specifying the maximum voltage and power supply variation range, and then adjust the relevant factors in the circuit to make the impedance of each part of the power system (related to frequency) approach the target impedance.