Five techniques to reduce power consumption in future ICs

　　Excessive power consumption has become a major obstacle to further scaling of semiconductor process dimensions and a serious threat to all progress in all areas of electronics - from driving smaller mobile devices to developing supercomputers.

　　While the root causes lie in immutable principles of physics and chemistry, engineers have developed a range of innovative techniques to mitigate current problems and potentially help revitalize the chip industry of the future.

　　The following discusses five technologies that can be used to reduce power consumption in future ICs. These technologies are currently under development and together they are expected to solve the power consumption problems that will be faced in the next decade.

　　Embrace collaborative design

　　Electronic design automation (EDA) tools enable design teams to co-design from the beginning to achieve optimized low-power designs. In fact, developers of the industry’s lowest-power processors and SoCs achieve their advantages not only by optimizing architecture and materials, but also by co-designing packaging, power supplies, RF circuits, and software to reduce power without sacrificing performance or increasing cost.

　　"Achieving low power consumption requires a comprehensive approach that covers technology, design methodologies, chip architecture and software," said David Greenhill, director of design technology and EDA at Texas Instruments (TI).

　　TI has used many advanced techniques to optimize each subsystem, thereby raising the bar for low-power devices, such as creating its own process technology to balance leakage current and active current performance in shutdown mode, or using voltage and frequency scaling techniques to define various power-saving operating modes.

　　"The first step is to confirm the product's goals from a performance and power perspective. Once these goals are determined, you can start using dedicated process technologies to provide the required performance without exceeding the device's power budget," said Randy Hollingsworth, TI's 28nm platform manager.

　　EDA tools have been key to achieving these lower power goals, but sometimes it takes some iteration around the design loop because power estimates using traditional EDA tools are only accurate near the end of the design cycle. For future ICs, accurate power estimates must be made early in the design cycle.

　　Some dedicated tool vendors have picked up the baton. For example, Atrenta, a California-based company, has launched a tool called SpyglassPower that performs power estimation, power reduction and verification using standard register transfer level (RTL) descriptions. These RTL descriptions are available from every major EDA tool early in the design cycle.

　　"Today, engineers want to estimate power earlier in the design cycle," said Peter Suaris, senior director of engineering at Atrenta. "You can no longer wait until the end of the design to estimate power. You have to co-design for power at the RTL level and make changes to the design to achieve energy savings from the beginning."

　　Atrenta claims that its dedicated power-saving tools can estimate the final power budget to within 20 percent, while the power-reduction tool can reduce the final design power by up to 50 percent.

　　Reduce operating voltage

　　Shrinking chip size often results in lower operating voltages, which in turn saves energy. For example, Samsung's latest 20nm 'Green Memory' chip saves 67% of power by reducing the operating voltage from 1.5V to 1.35V.

　　Processors and logic circuits operate at voltages even lower than in the first years of memory, but further improvements in semiconductor processes are inevitable as operating voltages drop below 1V. IBM, Intel, Samsung, TI, TSMC, and every other semiconductor manufacturer continue to improve processes to operate at lower voltages, but the pace of progress has begun to slow over the past few process generations.

　　The key is that the threshold voltage at which the transistor turns on is not consistent when using different wafers, because the process variation is negligible at larger sizes. And because the leakage current in the off state at a specific voltage varies greatly at different thresholds, the ideal chip actually uses a supply voltage customized to its characteristics.

　　Intel claims to have a better solution -- one that the company has spent nearly a decade perfecting. Intel uses a so-called tri-gate 3DFinFET transistor architecture that surrounds the transistor channel in three dimensions with three metal gates, subjecting the transistor to the gates' electric field. This technique offsets process variations that prevent operation below 1V.

　　"We have successfully demonstrated that our three-gate transistor structure can reduce the operating voltage to the 0.7V range, and it can be done even lower," said Mark Bohr, a senior engineer at Intel. "These are fully depleted transistors with a steeper subthreshold slope, which can turn off faster with less leakage current and turn on at a lower threshold voltage."

　　While well-funded semiconductor manufacturers are focused on emulating Intel's 3D architecture, some startups are working on developing new planar processes to restart the voltage scaling process for semiconductor manufacturers that lack the time and money to perfect 3D architectures. For example, SuVolta has invented an ultra-low voltage planar process for standard CMOS product lines.

　　Instead of using 3D gate depletion transistors, SuVolta uses an undoped channel (with doped threshold and guard bands) to avoid variations in doping. The deep depletion channel process can be implemented on standard planar CMOS product lines.

　　"By using a planar deep depletion channel process, we have successfully demonstrated that the supply voltage can be reduced to 0.6V, and it will be able to be reduced even lower in the future," said Scott Thompson, chief technology officer of SuVolta.

　　SuVolta has also secured its first license agreement, with Fujitsu Semiconductor, which will begin volume production later this year. Further announcements on this important licensing deal are expected later in 2012.

　　Intelligent adjustment function

　　Generally speaking, the lower the supply voltage and clock speed, the lower the power consumption. However, performance is also affected. Therefore, the latest microcontrollers and SoCs are beginning to seek to use intelligent power management units to automatically adjust the operating voltage and clock speed to match the workload.

　　"The basic idea of ​​power management is to independently adjust the supply voltage and clock speed of different parts of the chip to match their workload at any particular point in time while shutting down unused circuits," said Tyson Tuttle, who will take over as CEO of Silicon Laboratories.

　　Power management units are usually implemented as state machine modules that selectively reduce voltage and clock speeds for non-critical functions. But as semiconductor nodes become more advanced and more transistors are packed into chips, a concept called "dark silicon" -- where most chips are powered off until needed -- may be the forerunner of future semiconductor design.

　　"In the future, at more advanced process nodes, such as 22nm, SoCs will integrate more transistors that can be turned on at the same time," said Ely Tsern, CTO of Rambus. "The concept of dark silicon is to create many special-purpose functions on the chip, but only enable the required functions at any time, leaving other functions in a dark power-off state, doing nothing."

　　Intel is a leader in chip power management, with the ability to monitor core temperatures in detail at all times, allowing it to increase clock speeds (turbo mode) to improve performance or reduce speeds to save power.

　　But not all power management functions can be economically ported onto the chip. In fact, the smartest power management solution is to divide the tasks between the chip and the external power management unit. "There is a constant demand for external power management because there is a limit to what can be added to the chip in terms of power density," said Ashraf Lotfi, CTO and co-founder of Enpirion.

　　Enpirion specializes in stand-alone power management units that receive commands from a processor, such as reducing the processor's voltage when it enters sleep mode and quickly restoring the voltage when the processor is awakened.

　　Using 3D/optical interconnects

　　By shortening the length of interconnects and reducing their wire lengths, smaller driver transistors can be supported, thereby reducing the power consumption of the IC. The traditional way to shorten the length of interconnects is to add metal layers, so some chips currently have as many as 10 metal layers.

　　However, the latest innovation in interconnect layer design is three-dimensional through-silicon vias (TSVs), which allow memory chips to be stacked on top of processors. This technology reduces the interconnect length to the distance between chips, so there is no need for power-hungry driver transistors and long printed circuit board interconnects. However, TSVs are not economically viable, and most chip manufacturers are currently delaying TSV schedules.

　　“While through-silicon vias (TSVs) do reduce power by shortening trace lengths, they are a very expensive solution,” said TI’s Greenhill. “To be economical, TSVs need to be able to make up for other deficiencies, such as interface performance, to make their cost justifiable.”

　　Xilinx Inc. is a company that understands how to strike the TSV cost/performance balance and is delivering the first commercial chip using TSV. Compared to soldering individual components on a PCB, Xilinx's cost-effective approach not only reduces chip power consumption but also improves performance. It also reduces BOM costs for Xilinx's customers, said Ephrem Wu, senior director of Xilinx.

　　Xilinx has sidestepped the problem of soldering individual FPGAs to a PCB by using a silicon interposer that can interconnect four high-density FPGAs in a single package.

　　This technology not only improves performance, but also reduces power consumption to 19W, compared with 112W for traditional PCB solutions. Another front-end technology is to use optical transceivers. For example, IBM's Power7 supercomputer uses on-board photonic interconnects generated from traditional optical components. Future chips are likely to use dedicated optical solutions provided by Kotura and other companies, moving photonic functions to tiny optical chips that can attach processors and memory chips.

　　"Our low-power silicon germanium devices integrate lenses, filters, modulators and all the other optical components you need on a single chip," said Arlon Martin, vice president of marketing at Kotura.

　　Kotura's silicon photonics process enables it to integrate a conventional optical transceiver unit, which is about the size of a cigarette box and costs about $10,000, into a $500 package the size of the latest iPhone, using 4 to 20 times less power. Kotura also demonstrated that its SiGe transceiver can transmit optical signals through the air gap between stacked CMOS chips, ultimately forming a high-speed, low-power optical data channel between the stacked chips, suitable for replacing PCB traces.

　　Trying out new materials

　　Using materials with higher mobility can also reduce power consumption. For example, magnetic materials have been added to the standard CMOS product line, and "magic" materials such as carbon nanotubes and graphene are beginning to emerge.

TI has added magnetic materials to its CMOS product line to make embedded microcontrollers　　with ferroelectric RAM (FRAM) . FRAM, licensed from Ramtron International, is more convenient than flash memory because it is nonvolatile and supports random access.

　　"Compared to flash memory, our non-volatile FRAM is more energy efficient in reading and writing," said Baher Haroun, CTO of TI's wireless business unit.

　　Enpirion has also introduced magnetic materials into its CMOS product line and plans to start manufacturing integrated inductors and transformers for its power management chips in 2012. Currently, inductors and transformers cannot be integrated more economically on chips that must operate at high frequencies, but Enpirion's proprietary magnetic materials have been designed to solve this problem.

　　“We have combined different metal alloys to allow our magnetic materials to operate at very high frequencies while maintaining high energy efficiency,” said Enpirion’s Lotfi.

　　Meanwhile, Semiconductor Research recently funded a joint research project between IBM and Columbia University in the United States to integrate inductors into processors. The company claims that it can adjust the supply voltage in nanoseconds through the chip voltage regulation function to achieve workload matching, thereby reducing energy consumption by up to 20%.

　　Other near-term materials that may be added to the CMOS product line in the near future include indium gallium arsenide (InGaAs), which Intel plans to use to enhance the channel on future three-gate transistors, a move it says could reduce operating voltages to 0.5V.

　　However, in the long term, carbon nanotubes and flat versions of graphene are likely to become the materials of choice for future ultra-low power components.

　　In the laboratory of Georgia Institute of Technology (GeorgiaTech), it has been proved that the interconnection performance of graphene exceeds that of copper. IBM has also demonstrated that low-power, ultra-high-speed transistors can be manufactured using carbon nanotubes or graphene materials. TI recently demonstrated that graphene can be manufactured at the wafer level.

　　Intel has conducted research on using carbon materials to achieve higher electrical mobility, but has concluded that these materials are not ready for commercial use.

　　"Carbon interconnects using nanocarbon or graphene have very attractive properties," said Intel's Bohr. "However, while the bulk material has lower resistance, the resistance of the connection path is not low. This is a very promising material, so I expect to see more industry research in the next few years."