Research on FPGA testing method based on test system

1 Introduction

At present, most FPGAs use the technology based on lookup tables, which are mainly composed of programmable input/output units (IOBs), programmable logic units (CLBs), programmable routing resources (PI), SRAM for configuration, BlockRAM and digital delay-locked loops (DLLs). To test FPGAs, it is necessary to analyze the structure of the resources that may be contained inside the FPGA, configure the FPGA into a circuit with specific functions through a process of test configuration (TC) and vector implementation (TS), and then test the circuit at the application level to complete the function and parameter test of the circuit.

2 FPGA Configuration Method

There are many methods to choose from for configuring FPGA, including boundary scan configuration method, Xilinx's dedicated SPI/BPI FLASH configuration method, System ACE configuration method, CPLD+third-party FLASH configuration method, and system direct loading of configuration vector configuration method. The boundary scan method is mainly suitable for online configuration and debugging. The Xilinx dedicated Flash configuration method can only store a section of configuration code in FLASH at a time, which is not suitable for repeated configuration test processes. The System ACE method requires a dedicated System ACE control chip and CF card, and its application is more complicated. The latter two methods are mainly suitable for system testing.

2.1 Test system direct configuration method

When the test system used is more advanced, such as Teradyne's UltraFLEX, the system has a test frequency of up to 500 MHz, up to 1024 test channels, and a test vector depth of up to 128 M. The system can be used to directly load binary configuration vectors to configure the FPGA.

The method can complete multiple "configuration-testing" processes of FPGA chips in the same operation process. The method is simple to operate, improves the test efficiency of FPGA chips, and can realize industrial testing of FPGA chips.

2.2 CPLD+third-party FLASH configuration method

When the configuration code of the FPGA to be tested is relatively large and the vector depth of the test system (ATE) is insufficient, the CPLD+third-party FLASH configuration method can be used, and its structure diagram is shown in Figure 1.

The design of CPLD is the most important part. The functional modules it implements include interface module, control module and address generator module. The interface module realizes communication with the test system, receives test system instructions and processes them accordingly, and feeds back the working status to the test system; the control module provides control timing commands and manipulates the entire configuration process; the address generator module provides data addresses for reading flash memory data. The functional modules inside CPLD are implemented using hardware description language.

Flash is a storage device for configuration files. Multiple hexadecimal configuration files are pre-programmed into Flash. FPGA is the target device configured in the system.

This method uses ATE to control CPLD to read configuration codes in different address ranges in FLASH to configure FPGA, and then performs function and parameter tests on the configured FPGA without powering off.

3 FPGA Configuration Mode Selection and Configuration Code Generation

3.1 FPGA Configuration Mode Selection

There are many configuration modes for FPGAs, and the configuration modes of different series of FPGAs are somewhat different. The main configuration modes are: master serial mode, slave serial mode, master parallel mode, slave parallel mode, and boundary scan mode. Different configuration modes can be selected by setting the three mode selection pins M0, M1, and M2. The configuration modes are shown in Table 1.

Most of the time spent on testing FPGAs with a test system is spent on configuration, which can range from a few milliseconds to tens of seconds depending on the size of the configuration code. In order to increase the configuration speed, we configure the FPGA in slave-parallel mode, which can save the test configuration time to the greatest extent. Taking the Virtex-II series FPGA as an example, its slave-parallel configuration mode schematic is shown in Figure 2.

The FPGA configuration code needs to be written in the Xilinx ISE development environment to generate the required binary format configuration file, as shown in Figure 3.

In the figure, lines 1 to 7 belong to the file header and need to be deleted. Lines 8 to 9 are the start mark of the configuration data: FFFFFFFF AA995566, and the rest are configuration data.

The data width of the configuration file is 32 bits, and it needs to be modified according to the configuration data width of different FPGA series. Taking the Virtex-II series as an example, its slave mode data width is 8 bits, and we need to write an application to convert it into 8-bit wide data. The configuration data bit order is shown in Table 2. Taking 8-bit wide data as an example, D0 is the highest bit.

4 FPGA Configuration and Test Process

The FPGA configuration process mainly consists of four steps: clearing the configuration memory, initialization, configuration, and startup. Taking Virtex-II FPGA as an example, the timing requirements of the configuration process are shown in Figure 5: After the system is powered on, a low signal is given to the PROG_B pin, and the FPGA begins to clear the configuration memory. The FPGA pulls the INIT_B pin and the DONE pin low. When the configuration memory is cleared, INIT_B will become high. If CS_B is low and valid, the configuration data can be transmitted to configure the FPGA. When the DONE pin changes from low to high, it indicates that the chip configuration is complete.

When testing FPGA with a test system, the configuration code and test code can be made into different pattern files, and the configuration process can also be used as a functional test item, so that the FPGA circuit under test can be repeatedly configured and tested. The configuration pattern file is shown in Figure 5.

After the FPGA is configured, it has certain functions and can be functionally and parametrically tested like other circuits.

5 Conclusion

This article introduces the FPGA configuration method, configuration mode selection and configuration code generation method in detail, and takes the Virtex-II series FPGAXC2V250 as an example to introduce the configuration and test process of FPGA using the test system Ultra-FLEX in detail. This method can be widely used in the testing of various FPGAs, has strong versatility, and is of great significance for the realization of industrial testing of FPGAs.