How to use GaN: Drivers and layout considerations for GaN FETs

In our previous article, we discussed the advantages of GaN FETs and their potential to achieve higher efficiency and faster switching speeds not possible with silicon MOSFET devices. This chapter will explore how to utilize GaN FETs and consider driver and layout requirements to improve the performance of engineers’ designs.

Driver considerations

GaN FETs operate in the same way as traditional silicon devices, with a few exceptions, most importantly the maximum gate voltage of 6 V. To achieve the highest performance from GaN FETs, we recommend using a 4 V to 5 V driver, as shown in Figure 1. Due to the lower maximum gate voltage of GaN devices, a gate drive circuit with adjustable voltage is recommended to ensure safe operation. We have worked with Texas Instruments to develop a family of drivers designed to simply and reliably address the challenges of driving GaN transistors. This driver family helps designers easily adopt GaN FETs in most applications.

Figure 1: On-resistance vs. gate voltage of GaN FET at different temperatures

Layout Considerations

Due to its high frequency, low on-resistance and low package parasitic inductance, GaN FETs have the potential to deliver performance that is not available with current silicon (Si) technology. In addition, due to the higher switching speeds and lower package parasitic inductance of GaN devices, the PCB layout can affect the converter performance. As shown in Figure 2a, the common source inductance (LS) and high-frequency power loop inductance (LLOOP) have a significant impact on the converter power consumption, so these inductances in the PCB layout must be minimized. To demonstrate the impact of high-frequency loop inductance on circuit performance, Figure 2b shows the efficiency of an experimental prototype with loop inductances ranging from 0.4 nH to 2.9 nH. As can be seen in Figure 2, increasing the loop inductance in the PCB layout can reduce the efficiency by almost 5% in GaN FET-based designs.

Figure 2: 1) Synchronous buck converter with parasitic inductance 2) Effect of high-frequency loop inductance on efficiency for designs with the same common-source inductance VIN=12 V, VOUT=1.2 V, Fs=1 MHz, L=150 nH, eGaN FET: T: EPC2015 SR: EPC2015, MOSFET: T: BSZ097N04LSG SR: BSZ040N04LSG)

Another effect of the extremely high switching speed of GaN FETs is that, compared to slower, higher parasitic inductance silicon MOSFET devices, GaN transistors can cause voltage overshoot in circuits with less high-frequency loop inductance. Reducing the high-frequency loop inductance can reduce overshoot, increase the input voltage capability of the device, and reduce EMI. Figure 3 compares the drain-to-source voltage waveforms of two GaN FET-based synchronous rectifier designs: the first design with a high-frequency loop inductance of 1.6 nH has 100% of the input voltage overshoot; the second design with a high-frequency loop inductance of 0.4 nH has only 25% of the input voltage overshoot.

Figure 3: Switching node waveforms for two designs: Design 1: LLOOP≈1.6 nH Design 2: LLOOP≈0.4 nH (VIN =12 V, VOUT=1.2 V, IOUT=20 A, Fs=1 MHz, L=150 nH, eGaN FET: T: EPC2015 SR: EPC2015)

Optimize layout

The most important parasitic inductance to reduce is the common source inductance, which is the inductance of the high-frequency power loop and the gate driver loop. The PCB layout will increase the common source inductance. To minimize the common source inductance, it is recommended to design a layout where the gate driver loop and the high-frequency power loop rarely affect each other. Figure 4a is an example of a layout, with the gate driver loop in red and the high-frequency loop in yellow, which will only communicate next to the GaN FET. The GaN FET package can minimize the common source inductance to an ultra-low internal package inductance.

In the high-frequency power loop, most converter designs use two traditional methods of designing the printed circuit board layout, namely the lateral and vertical high-frequency power loop design. Figure 4a is a top view of the lateral power loop design, with the high-frequency loop in yellow. The input capacitors and devices are placed on the same side of the printed circuit board, and the current flows horizontally on the top layer of the circuit board. All components should be arranged closely to reduce the physical size of the high-frequency loop. Figure 4b shows the side view of the vertical power loop design, where the input capacitors and devices are placed on opposite sides of the printed circuit board, and the capacitors are generally placed directly below the devices, thereby minimizing the physical size of the loop. This layout is considered a vertical power loop because the power loop must be completed by the input capacitors and devices being connected directly through the through holes of the printed circuit board. There are advantages and disadvantages to these two designs, which we have discussed in detail in the "Optimized Layout White Paper".

Figure 4: Conventional PCB design with eGaN FETs a) Top view of lateral power loop b) Side view of vertical power loop

To improve performance, the strengths of traditional lateral and vertical designs can be exploited and their weaknesses suppressed. EPC has developed an optimized layout: We minimize the parasitic inductance of the printed circuit board. As can be seen from the side view of Figure 5a, a multi-layer printed circuit board structure is used with a low profile self-cancelling loop. This design uses the inner first layer as the power loop return path, which is directly below the power loop on the top layer, allowing a loop with the smallest physical size and a magnetic self-cancelling loop to be synthesized.

Figure 5: 1) Side view of the optimal power loop with eGaN FETs 2) Comparison of the efficiency of the optimal design with eGaN FETs and the optimal design with MOSFET devices (VIN=12 V, VOUT=1.2 V, Fs=1 MHz, L=300 nH, eGaN FET: T: EPC2015 SR: EPC2015, MOSFET: T: BSZ097N04LSG SR: BSZ040N04LSG)

Using the optimized power loop, the high-frequency loop inductance can be reduced by up to 40% to less than 0.4 nH compared to the traditional optimal PCB layout, which equates to improved performance. Figure 5b shows the efficiency comparison of a buck converter with 40 V silicon MOSFETs and 40 V GaN FETs using the optimized layout. We can see that the GaN FET-based design can improve efficiency by more than 3%. Since the optimized layout significantly reduces the high-frequency loop inductance, the GaN-based design can increase switching speed by up to 500% and reduce overshoot voltage by 40% compared to the baseline design with 40 V silicon MOSFETs.

Figure 6: Switching node waveforms of the best design with eGaN FETs and the best design with MOSFETs (VIN=12 V, VOUT=1.2 V, IOUT=20 A, Fs=1 MHz, L=300 nH, eGaN FET: T: EPC2015 SR: EPC2015, MOSFET: T: BSZ097N04LSG SR: BSZ040N04LSG)

Summarize

High-performance GaN FETs enable potential that cannot be realized with conventional silicon MOSFET technology – switching at higher frequencies and higher efficiencies. Due to GaN FETs’ improved quality factor and low parasitic inductance packages, a low parasitic inductance PCB layout is required to fully realize the device’s performance. EPC has developed an optimal layout that further enhances GaN FET technology advantages and achieves additional gains in efficiency, as well as the ability to operate at higher voltages.