Design of dynamic backlight source and its driving circuit based on FPGA

introduction

Most of the contemporary LCD displays use cold cathode fluorescent lamp (CCFL) backlight or LED static backlight. Since CCFL brightness is difficult to control and has a slow response speed, it causes energy waste and motion blur. Although LED static backlight has good effect, it also consumes a lot of energy. In addition, the constant brightness backlight reduces the contrast of the image and the display effect is not ideal. By analyzing the RGB pixels of the image and appropriately using a lower brightness LED backlight in certain areas, it can not only save energy, but also increase the contrast of the image display and eliminate the motion blur phenomenon.

1 Design scheme and its principle

The dynamic backlight source is a whole on the surface, but in fact, it has been divided into multiple areas when making the schematic diagram, and its brightness is controlled separately. It can be seen that the higher the density of the backlight, the more divided areas and the smaller the area, the better the overall display effect will be. However, considering the cost, economic value, manufacturing process, energy saving and other aspects, it can be seen that the number of lights cannot be infinite, and the divided areas will not be infinitely dense, but the most suitable design specification can always be found.

The RGB color model is a color standard in the industry. Through the RGB model, an intensity value in the range of 0 to 255 is assigned to the RGB components of each pixel in the image. RGB images only use three colors, mixed in different proportions, and theoretically present 16,777,216 colors on the screen. In this system, only the RGB components cannot directly obtain the brightness control parameter Ki we need. It is necessary to obtain the grayscale value of each pixel of the image through FPGA calculation and then calculate it.

The basic idea of ​​grayscale calculation for an image is to average the values ​​of the three RGB color components of each pixel. However, due to the sensitivity of the human eye, this approach is not very effective. Each component should have a certain weight. The calculation formula is as follows.

(1) is the grayscale calculation formula. The grayscale value of a pixel can be directly calculated from each RGB component. Of course, it can be enlarged or reduced as a whole, that is, multiplied by a common coefficient.

(2) is the formula for calculating brightness from pixel grayscale, where Tmax is the maximum transmittance, which is a fixed value in the same system and can be ignored, γ is the RGB pixel correction factor, and B is the backlight brightness value.

When the brightness of the backlight source becomes the original 1/λ, that is, B', in order to prevent the brightness of the grayscale C' pixel observed by the human eye from changing significantly, the values ​​obtained twice should be consistent, that is:

make:

Solving the equation yields:

In general, the grayscale adjustment is controlled by 8-bit data, that is, the grayscale value can be divided from 0 to 255 into 256 parts, each of which represents a grayscale level (the grayscale level of the driver chip used in this experiment is 4,096). So the light control parameter Ki can be:

Where Cmax is the maximum grayscale value in each segmented area, Ci is the maximum grayscale value in each corresponding area, and the calculated regional light control parameter Ki is used to adjust the output of the FPGA to adjust the backlight brightness, so that the RGB values ​​of each pixel after correction can be obtained:

As shown in the scheme diagram, the horizontal and vertical synchronization signals and the corrected RGB signals output by the controller are finally transmitted to the LCD panel.

The main functions of SDRAM in the scheme are twofold: first, it is used to store the line and field synchronization information and RGB data information transmitted from the graphics controller when the FPGA is not processed in time; second, it is used to store the data processed by the FPGA and the information that the single LCD panel cannot process in time. The purpose of this design is to achieve the effect of no data loss and more timely information transmission.

2. Drive Circuit Design

In the selection of driver chip, we use TI's TLC5947, each channel is modulated by 12 bits PWM pulse width, with 24 output channels, so one data transmission cycle will receive 288 bits of data. The chip requires a voltage of 3.0~5.5V, and has a temperature control system. When the temperature of the chip is too high, it will automatically disconnect to protect the chip.

As can be seen from the pin 25 of the chip, this chip supports cascading, and multiple chips can work together to drive a larger display screen. From pin 1 to pin 24, each output channel is controlled by 12-bit input data. It contains a 4MHz crystal oscillator. The ratio of the input data to 212 or 4,096 is the duty cycle of the output pulse, thereby realizing PWM modulation of the corresponding area of ​​the backlight source. From this, we can see that TLC5947 divides the grayscale into 4,096 levels. We can subdivide the brightness of the backlight source on a large scale and precisely to achieve a better dynamic backlight effect.

Figure 2 TLC5947 pinout

The resistance in the driving circuit is determined by the current of the driven LED lamp. For details, please refer to the TLC5947 configuration table (as shown in Table 1). The chip has strict timing requirements for input signals such as SCLK, XLAT, and BLANK. The capacitor between the power supply and the ground mainly plays a filtering role, so try to choose a larger value.

Table 1 Relationship between configuration resistance and drive current

Figure 3 Backlight drive circuit

3 Software Design

The control signal of this chip is provided by the development board of Altera, model EP1C3T144C8, and the crystal oscillator is 50MHz.

From the experimental results, the data transmission mechanism of this chip is as follows: in each transmission cycle, every time the SCLK rises, 1 bit of data will be read from the SIN port and stored in the register. At the falling edge of SCLK, the read data will be transmitted from SOUT (the data is still retained internally) to the next level until 288 bits of data are read. Each 12 bits is a group and sent to their respective channels, and each group of data is read first in a higher position and then arranged in sequence. For example, the read data is arranged in chronological order as 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, and the corresponding control signal is 100000000000, then the duty cycle of the control channel is:

According to the principle of equal PWM modulation area, the effective voltage is approximately half of the supplied voltage.

According to the requirements of the simulation conditions, the SCLK clock signal needs to be at a low level for a period of time after receiving 288 bits, so as to meet the timing requirements of the chip as much as possible. In addition, the control signal BLANK needs to have a high level transition when it is idle in each cycle (when no data is transmitted), so that the data in the latch can be cleared to receive a new round of control data, otherwise, the brightness of the light will be obviously dim.

The RGB data is processed by the FPGA and converted into corresponding grayscale values, and then the corresponding light control parameter Ki is calculated (the grayscale levels we can divide do not exceed 4,096) and transmitted to the SIN of the TLC5947, which can realize dynamic backlight adjustment.

Figure 4 Input and output signal settings

Figure 5 Signal simulation diagram

Figure 6 PWM modulation output waveform

4 Conclusion

Through theoretical analysis and experimental testing, the dynamic backlight adjustment control system performs well in energy saving and improving image display contrast, which has good application prospects in today's world where energy conservation and emission reduction are emphasized and a harmonious society is built, as well as in the future development of LCD displays.

Figure 7 shows the effect of dynamic backlight adjustment obtained through FPGA control and image pixel control. It can be seen that under the previous LCD static backlight condition, the brightness of all backlight LEDs will be the same as the brightest (lower right corner), but now we divide it into different areas, so that each area has its own optimal brightness, without having to use the brightest point of the entire image as the standard, and it does not affect the display effect. In this way, we have achieved our expected purpose of dynamic adjustment.

Figure 7 Backlight effect diagram