Design and implementation of telemetry cabin signal source

Abstract: In order to detect whether the telemetry cabin can work normally, various input signals must be provided to it to simulate the actual measured signal. Therefore, the design of a signal source with good performance plays a vital role in the telemetry cabin. Here, a design scheme and implementation method of a telemetry cabin signal source based on FPGA are given. Practice has proved that the design and implementation method have unique creativity. This signal source not only has stable performance, but also has good flexibility and meets the use requirements.
Keywords: telemetry cabin; signal source; FPGA; VHDL

0 Introduction
The telemetry cabin is an indispensable key test component in the development of missiles. It provides an important guarantee for the smooth development of missile systems. In order to improve safety and reliability, the telemetry cabin product must pass detection and debugging before use. The telemetry cabin signal source sends various excitations to the product to be tested in real time according to the test requirements to simulate the actual measured signal of the missile telemetry cabin. The telemetry cabin product will process the received excitation signal accordingly, and then output data from its output end. These data will be collected inside the telemetry cabin. Through the analysis of the ground receiving system software, it can be judged whether the telemetry cabin product has any faults. It can be seen that the signal source is a very important component of the telemetry cabin detection system. This article mainly discusses the design and implementation of this signal source.

1 Design requirements
The signal source needs to provide serial image data, parallel data, serial RS 422 data, and analog signals for the telemetry cabin. These signals can be output separately or in combination. The analog signal can output a pulse signal with an amplitude of -10~+10 V and a frequency of 100~40 kHz. The
signal generators on the market are generally used to generate relatively simple signals, which cannot meet the needs of this system. Therefore, a programmable signal source will be designed according to the special requirements of this system.

2 Design scheme
The design method of the digital signal source is adopted, mainly with FPGA programmable chip as the core, supplemented by the necessary level conversion circuit to form a programmable signal source. The control logic is implemented by the FPGA programmable chip. FPGA mainly realizes three functions through internal logic: generating the frequency reference signal required for the analog signal; generating the accompanying signal of parallel data and image data, and generating parallel data and serial RS 422 data and serial image data. The analog signal is amplitude-adjusted by the power amplifier circuit. The digital signal is level-converted through the interface chip.
The signal source circuit board consists of a power conversion module, a programmable logic device, an LVDS interface chip, an RS 422 interface chip, an operational amplifier, and a bus driver, etc. The hardware circuit block diagram is shown in Figure 1.

The FPGA uses Altera's Cyclone series EP1C6. Cyclone FPGA is the most cost-effective and cheapest FPGA on the market. It has a capacity of 5,980 logic units and up to 92,160 bits of embedded RAM. It supports various single-ended I/O standards such as LVTTL, LVCMOS, PCI and SSTL-2/3. The FPGA has up to 185 I/O ports, which can be freely controlled and defined through VHDL language programming, which is convenient for layout and routing during PCB layout design. In addition, the speed of FPGA hardware is nanosecond level. The processing of each functional module in the VHDL program is carried out in parallel, which not only solves the problem of multiple signal paths, but also can transmit and process high-speed data streams in real time and quickly. At the same time, with the help of EDA tool software Quartus, code writing, functional simulation and timing simulation are directly carried out, and the verification, addition and modification of hardware functions are completed simply and easily. The configuration device uses Altera's serial configuration device EPCS1, which is industrial-grade and low-cost, and provides in-system programming (ISP) and multiple programming capabilities, which are not available in one-time programmable devices, but its cost is even lower than that of one-time programmable devices, making it the perfect complement to the Cyclone series devices. The storage capacity ranges from 1 Mb, making it easier to match the optimal solution required for FPGA construction.
3 Design and Implementation
3.1 Serial Image Data
The transmission time of the whole frame is 10 ms (including the frame header and all valid data bits); at the beginning of each frame data transmission, two frame header check words FAF3EB90 are sent first, where the width of each word is no more than 200 ns (the check word is sent once per frame, so the interval between each group of check words is 10 ms), and then 16 384 (128 rows, 128 columns) words of original image data are sent, and the width of each data word is also no more than 200 ns, and the content of the word is 0000~4000 and sent cyclically; after the original image data is sent, 256 words of digital quantity need to be sent, the first two words are check words 050C146 F, 202 words are valid digital quantity information, the content of the word is 0100~0000 and sent cyclically, and the remaining information words are filled with zeros.
The signal timing diagram is shown in Figure 2.

YLVDSD: Send 16-bit data, transmit all data from the system to the image acquisition device, each data bit width is equal to half the clock cycle;
YLVDSS: Send synchronization signal, synchronized with each word, sent at the same time as the highest bit of the first data, with a width of half a clock;
YLVDSC: Clock signal, always maintained.
All data is based on line time, that is, a group of 128 data is sent every 62.5μs (counted based on the synchronization signal). A total of 130 lines are sent, of which 128 lines in the forward direction send image data and two lines in the reverse direction send information words.
The program is written in VHDL language to make the FPGA output three LVTTL level signals with fixed timing, which are converted into LVDS signals after passing through an LVDS interface chip.
The LVDS interface chip uses National Semiconductor's DS90C031, which is a four-way LVDS line driver powered by a single power supply of 5 V.
3.2 Parallel data
Parallel data is sent along the byte multiplexing channel in the form of information frames. The information update cycle is 10 ms, and 128 information words are transmitted in each update cycle. These information words are divided into 2 subframes, each with 64 words, and one subframe is sent every 5 ms. The information word is 24 bits, including 8 bits of address and 16 bits of data. In this way, the digital telemetry information rate of parallel data is 307.2 Kb/s.
The structure of the digital telemetry information word of parallel data is shown in Figure 3.

Parallel data is transmitted in 8-bit parallel mode. The three bytes of each information word are sent three times along the 8-bit bus in time-sharing mode. Different combinations of the accompanying signals CS1 and CS2 constitute the distinguishing marks of the address byte, the high-order data byte and the low-order data byte. The signal WR indicates the transmission of information. The address is sent cyclically from 00 to 7F, and the data is sent cyclically from 0000 to 9FFF. The 8-bit bus signal, accompanying signal and write signal transmission are all driven by 245. The information transmission timing represented by the change of the signal line voltage of these signals is shown in Figure 4.

As can be seen from Figure 4, the transmission time of an information byte is 2μs, and the transmission time of an information word is 6μs. The interval time between two adjacent information words is 10μs.
The parallel data information is sent after completion within a 5 ms cycle, and the time for sending information in each cycle is about 640μs.
The program is written in VHDL language to make the FPGA output 3 LVTTL level signals with fixed timing, which are converted into TTL level parallel data signals after passing through 2 bus drivers.
3.3 Serial RS 422 data
There are 3 channels of serial RS 422 data. The LVTTL level data that complies with the RS 422 protocol is generated through the FPGA VHDL program, and the level conversion is performed through the RS 422 interface chip.
The RS 422 interface chip uses Maxim's MAX1484, which is a 1-receive 1-transmit driver and full-duplex.
(1) The baud rate of the first DF422 channel
is 500 Kb/s, each frame is 2.5 ms, and the frame length is 9 bytes.
(2) The baud rate of the second ZW422
is 240 Kb/s, each frame is 1 ms, the frame length is 12 words, 8 bits/word.
The data format is:
1 start bit + 8 data bits + 1 stop bit + 10 idle bits, where: 8 bits of data are low bits first and high bits last.
(3) The baud rate of the third YX422
is 200 Kb/s, the message block update frequency is 400 Hz, each message block has 6 words, and each word has 11 bits:
1 start bit + 8 data bits + 1 parity bit + 1 stop bit
3.4 Analog signal
By dividing the 48 MHz external clock to generate a fixed frequency pulse square wave with an amplitude of 0 to 3.3 V, a high-speed operational amplifier is used to generate a linear proportional amplifier circuit to adjust the amplitude.
The operational amplifier uses AD's AD824, which supports single power supply and is a low-power field effect transistor input operational amplifier.
3.5 Circuit design
In the design, a variety of measures are taken to ensure the normal operation of the signal source under various conditions.
(1) Adopt 4-layer PCB design to avoid using too many discrete devices, reduce the size of the equipment, shorten the leads, and improve reliability;
(2) Add filter capacitors to the power supply and device power pins to reduce the impact of power supply noise on the device and circuit board;
(3) Reasonable layout and wiring of the printed circuit board to reduce the mutual interference between various signals;
(4) The differential signal line d+ and d- to the interface does not exceed 30 mm, and the length difference between the two signal lines is controlled within 2 mm to ensure that the LVDS data transmission bandwidth requirements are met;
(5) In the circuit design, measures are taken to maximize the system's isolation from various interferences and the suppression of sudden large signals to protect the system from reliable operation. The output circuit is connected in series with a protection resistor to ensure that the circuit is intact when the output is short-circuited.

4 Conclusion
In summary, the design and implementation of the multi-channel programmable signal source in the telemetry cabin are mainly introduced, and several key technologies in the design are studied and demonstrated in detail. By using FPGA as the design core, writing VHDL programs to generate the main logic functions, and attaching peripheral level conversion chips to realize various types of signal outputs. Practice has proved that this signal source can fully simulate the signals measured by the telemetry cabin and meet the design requirements.