VCO Design for Ethernet Physical Layer Clock Synchronization PLL

Abstract: A high-bandwidth, low-noise voltage-controlled oscillator (VCO) based on Ethernet physical layer clock synchronization is studied. The VCO adopts a cross-coupled current-starved ring oscillator. By cascading 11 loop circuits and improving its control voltage conversion circuit, the output frequency range of the VCO is optimized and the phase noise of the output clock is reduced, which fully meets the performance indicators of the Ethernet physical layer chip clock circuit. The simulation results based on TSMC 3.3 V 0.25 μm CMOS process show that when the center frequency is 250 MHz, the voltage-controlled gain is 300 MHz/V, the linear region covers the range of 60 to 480 MHz, and the phase noise is -108 dBc at a deviation of 600 kHz from the center frequency.
Keywords: VCO; ring oscillator; current-starved; clock synchronization

0 Introduction
In Ethernet, the physical layer chip (Physical Layer Interface Devices, PHY) is a key component that connects each network element to the physical medium. Responsible for completing the functions in Layer I of the OSI (Interconnection Reference Model), that is, providing the mechanical, electrical, photoelectric conversion and procedural means required for physical connection for bit transmission between link layer entities. Its functions include establishing, maintaining and dismantling physical circuits, realizing transparent transmission of physical layer bit streams, etc. The physical layer includes four functional layers and two upper layer interfaces. The two upper layer interfaces are the physical medium independent layer interface (MII) and the physical medium dependent layer interface (MDI). The upper layer of the MII is the logical data link layer (DLL), and the lower layer of the MDI is directly connected to the transmission medium. The normal operation of these sublayers is inseparable from a stable and accurate clock synchronization signal. In the clock synchronization application of the physical layer chip, the PLL is required to have a wide output clock bandwidth coverage, good voltage control frequency linearity, and high spectrum purity. In the PLL design process, VCO is the most critical design link, and its performance will directly determine the quality of the PLL design work. In recent years, VCO phase noise has been studied more and more deeply, and various low-noise VCO structures have emerged. The cross-coupled current-starved VCO mentioned in the literature is one of them. Current starvation means that the current of a circuit unit is clamped by the current source and cannot reach its maximum value. Based on this, this paper adopts an effective control voltage conversion circuit to ensure the advantages of the original circuit while expanding the linearity, improving the anti-noise ability, and effectively reducing the phase noise.

1 Working principle of VCO delay unit
Figure 1 shows the single-stage structure in the current-starved VCO. PNP tube M1 and NPN tube M2 are components of the delay unit. Ictrl is used to control the discharge current Id1 and the charging current Id2 of the capacitor. They constitute each level of the ring oscillator. Ictrl controls the current flowing through the M1 tube and the M2 tube, so the delay unit composed of the M1 tube and the M2 tube is in a current-starved state. Each level of the delay unit is in a current-starved state. The current of each level is mirrored by the same current source, so Id1=Id2 and the current size is controlled by the input control current Ictrl.

There are two main reasons for the inversion delay: one is the charging time of RC; the other is the preset voltage of the inverter. Both of these delay times can be achieved by adjusting the width-to-length ratio. The number of ring inversions must be an odd number so that the circuit will not lock and cause oscillation failure. The number of oscillator stages in a differential structure can be an even number, as long as one of the stages is connected to non-inverting. This flexibility is an advantage of differential circuits over single-ended circuits.

2 Current-starved VCO
As shown in Figure 2, the VCO is a differential current-starved ring oscillator structure composed of 11 single-ended inverting delay units, 11 differential inverting delay units, and a cross-coupled output structure converted to a single-ended output, and its oscillation voltage can reach the full swing. Cross-coupled, gate-grounded P tubes, an inverter is added between the two rings, so that their output signal phase difference is 180°. In order to synchronize the two oscillators immediately when powered on and maintain an output phase difference of 180°, the size of the two gates must be set relatively large to have sufficient driving capacity. This structure can effectively suppress the influence of environmental noise including power supply and substrate noise, and therefore has good noise resistance. When designing a ring oscillator, the capacitive load of each input and output point should be fully considered to ensure that the delay of each stage is the same, so that the oscillation frequency of each input and output point can be the same.

In addition, since the channel length L determines the maximum operating frequency, the channel length should be increased as much as possible under the condition of meeting the maximum operating frequency index to reduce the circuit's sensitivity to process parameters, so that the circuit can still work normally even in the worst case. The control current of the first-stage inverter comes from the output voltage of the RC filter in the PLL. When designing the width-to-length ratio of the inverter, it is necessary to ensure that there is a sufficiently large control current adjustment range, and at the same time, the channel length should be long enough to eliminate the short channel effect. The substrate of the inverter MOS tube and the filter capacitor are connected to the same reference ground potential, so that the PMOS tube and the NMOS tube are not affected by ground noise. In the current path parallel to the control branch, the NMOS tube is a long channel tube, which provides a small bias current for the VCO, ensuring that the oscillator can still oscillate when the control tube works in the subthreshold state. The inverter capacitor tube is connected between the virtual ground line and VDD, and its function is equivalent to a capacitor. It can effectively limit the voltage fluctuation of the virtual ground line, thereby enhancing the anti-noise ability of the VCO. If a larger capacitance value is required, it can be obtained by connecting multiple tubes in parallel. However, this circuit needs to design a good voltage/current conversion circuit, that is, a control voltage conversion circuit.

3 Control voltage exchange circuit
The control voltage conversion circuit is shown in Figure 3. The working principle of this circuit is to proportionally scale the output voltage of the RC filter, that is, the input voltage of the conversion circuit, while keeping the oscillator control current range unchanged. This enables the oscillation control branch to provide a larger control current under the critical saturation working state, thereby improving the linearity of the high-frequency region and increasing the linear coverage frequency range of the VCO. In Figure 3, the control tube M1 is used for impedance conversion, M2 and M3 are used for voltage amplification, the first-stage inverting amplifier uses a PMOS tube to amplify a very small voltage, and the M3 tube is a second-stage inverting amplifier NMOS tube. This ensures that the output voltage and the input voltage have the same phase function. The bias circuit of the control voltage conversion circuit adopts a common source and common gate structure, which is completely suitable for low-voltage circuits. This structure not only enhances the interference ability of the conversion voltage on the power supply, process, temperature dependence, and output current noise, but also suppresses the influence of power supply noise on the VCO input voltage. M1, M13, and M18 form a low-voltage common-source common-gate structure. At this time, the gate voltage of M1 is (Vth+2Vds), which is provided by the bias branch composed of M18 and M22. By isolating the control tube and the oscillator control current, the influence of the voltage oscillation generated by the oscillator on the control tube can be further suppressed, and the fluctuation of the control current can be reduced, thereby reducing the frequency jitter of the VCO output, greatly reducing the phase noise of the VCO output, and effectively improving the spectrum purity of the VCO output.

4 Simulation results
The power supply voltage of the circuit is 2.5 V. Using the Spectre simulation tool, the output frequency and control voltage characteristic curves and phase noise characteristic curves of the VCO circuit are shown in Figures 4 and 5. Figure 4 is the output phase noise curve of the VCO, which shows that the low-frequency 1/f noise is well suppressed. The phase noise at a deviation of 600 kHz from the center frequency is -108 dBc/Hz. Figure 5 is the output frequency and control voltage characteristic curve of the VCO, which shows that the control voltage adjustment range of the VCO is 0.6~2.0 V, the linear frequency coverage range is 60~480 MHz, and the voltage-controlled gain is 300 MHz/V, which meets the clock frequency requirements of the Ethernet physical layer chip. Table 1 shows the performance parameter indicators of the entire VCO.

5 Conclusion
This paper designs a high-bandwidth, low-noise VCO suitable for Ethernet physical layer chip clock synchronization PLL, using a cross-coupled current-starved differential ring oscillator with good noise immunity. The simulation results show that under the same input noise and environmental noise, when the center frequency of the VCO in this paper is 250MHz, the frequency coverage range of the voltage-controlled gain linear region is 60~480MHz, and the phase noise at a deviation of 600kHz from the center frequency is -108dBc/Hz, which is significantly improved compared with the performance of the traditional inverter delay unit ring VCO in the literature. It shows that the improved circuit has a wider frequency adjustment range, better linearity and lower phase noise, which fully meets the performance requirements of the Ethernet physical layer chip clock synchronization PLL.