Two DDS Implementations Based on FPGA

DDS (Direct Digital Frequency Synthesizers) is widely used in civilian and military equipment such as radar systems, digital communications, electronic countermeasures, and electronic measurements. It is a new type of frequency synthesis technology developed with the rapid development of semiconductor technology and digital technology . Compared with the traditional VCO+ PLL analog method of generating the required frequency, DDS technology has the advantages of high frequency resolution , low phase noise, wide bandwidth, and good spectrum purity. These technical indicators are crucial in a system and determine the success or failure of a system.

1 Basic Principles of DDS

1.1 Basic principles of frequency synthesis

DDFS is based on the corresponding relationship between the phase and amplitude of the cosine function. Starting from the phase, different phases give different voltage amplitudes, and then after D/A conversion and filtering, an analog signal with a certain frequency and modulation frequency is finally obtained. It can be seen that DDS is composed of many functional modules, as shown in Figure 1.

If the phase accumulator has N bits, the clock frequency is fclk, and the frequency control word is FCW, the N-bit phase accumulator can divide the clock frequency by 2N, so the accuracy of the DDS can reach:

The frequency control word is used to control the step of the accumulator. The step of the accumulator is . Assuming the initial phase offset △φ=0, the output of the phase accumulator after N clock cycles is θ=2π*FCW*N*(1/2N). When the phase step is △0, completing a phase change of 2π is equivalent to completing an output cycle, so 20/△θ*Tclk=T0, that is:

It can be seen that by adjusting FCW, the output frequency can be changed arbitrarily as required, thus achieving the purpose of frequency synthesis.

1.2 Principle of direct reading DDS

The working process of the direct reading method (DDWS) is to directly sample and quantize the required DDS waveform using Matlab, then store the quantized data directly in the BlockRAM of the FPGA , and then read the data directly from the BlockRAM under the control of the clock frequency, and output the original waveform after D/A.

2 Digital Implementation

2.1 Digital Implementation of DDFS

Since the parts before D/A are all digital parts, in order to analyze the implementation process of its principle digital control, refer to the structure shown in Figure 2.

The phase accumulator is composed of an adder and a register . Assuming that the accumulator bit number N=6, then 000000 represents 0 radians, 000001 represents radians, and the corresponding 000010 represents (2π/64)*2 radians, and 111111 represents (2π/64)*63 radians. If the frequency control word FCW=000011, and the initial phase in the accumulator is O, then the binary sequence formed after N=21 clock cycles is 000000, 000011, ..., 111111, and the corresponding phases are O, (2π/64)*3, ..., (2π/64)*63. When the 22nd clock cycle arrives, the adder overflows, all bits are reset to 0, and another cycle begins. The lookup table can be made with BlockRAM in FPGA. The previous binary sequence is used as the address, and the amplitude value corresponding to the phase is stored as the value corresponding to the address. In this way, the corresponding amplitude can be read from BlockRAM through the binary sequence under the control of the clock frequency, and the required analog waveform is obtained after D/A. Figure 3 is the RTL level circuit diagram after FPGA synthesis.

2.2 DDWS digital cash purchase

The digital implementation of DDWS is relatively simple. The data sampled and quantized by Matlab is directly saved in .BAT data format. Then, a ROM is generated in the FPGA using the BlockRAM of the IP core and the data is stored in it. In this way, the required data can be output according to the clock requirements.

Figure 4 is the RTL level circuit diagram after FPGA simulation.

3 Performance indicators of DDS

3.1 Frequency resolution

For frequency synthesis DDS, as long as the number of bits of the accumulator is large enough, the frequency resolution can be theoretically infinitely high. According to formula (1), if N = 39, fclk = 1, the resolution can reach 0.000 18 Hz. However, for direct reading, the resolution is limited by the hardware D/A speed. Generally, if the acquisition and recovery are performed at four times the frequency speed, the resolution can only reach 0.25 Hz.

3.2 SFDR

The most commonly used parameter for evaluating the working performance of a DDS is the out-of-band rejection ratio (SFdR), which refers to the difference between the spectrum amplitude of the effective signal and the maximum value of the noise spectrum amplitude. In actual spectrum synthesis DDS, there is a phase break process between the output of the accumulator and the lookup table. If the output A of the accumulator is N bits and the input B of the lookup table is M bits, N>M is generally the case. This is to save space in the lookup table. It is precisely because of this phase break that the SFDR is reduced, causing the performance of the DDS to deteriorate. The above parameters can be estimated based on actual requirements. For example, to generate a 4 MHz sinusoidal signal with a resolution of 0.4 Hz and an out-of-band rejection ratio of 60 dB, the clock frequency is 100 MHz. Then according to formula (2), N=11 can be obtained; according to actual experience, each bit of the lookup table can produce a rejection ratio of 6 dB, so M=60/6=10 b. Since direct reading DDS does not have the problem of phase break, it can often obtain a relatively good SFDR.

3.3 Signal-to-Noise Ratio

Since SFDR is only related to the spectrum amplitude of the maximum noise, the same SFDR may have different spectrum purity. For this reason, another DDS performance indicator is introduced - signal-to-noise ratio (SNR). The signal-to-noise ratio refers to the ratio of signal power to noise power. Since it involves all noise, it is closely related to spectrum purity. For DDS with high frequency resolution, the noise energy is low, the signal-to-noise ratio is large, and the spectrum purity is good.

4 Matlab simulation results

According to the simulation data of the FPGA of the two DDS, the waveform can be output through Matlab simulation, as shown in Figure 5 and Figure 6.

The comparison of the above three performance parameters can be clearly seen from the figure. The SFDR of the direct-reading DDS is much larger, the spectrum purity is also good, and the frequency resolution of the synthesis method is high.

5 Conclusion

From the above comparison, we can find that direct reading is a very good choice in practical applications. However, this method can only output limited pre-set frequencies and modulation rates, and is not universal and suitable for specific occasions. The frequency-synthesized DDS can synthesize any frequency and modulation rate, and can also achieve the required indicators through certain measures, so this principle is a universal principle and is widely used by scientific researchers and DDS manufacturers. In radar systems (such as altimeters and scatterometers), only one or several specific modulation rates, bandwidths, and frequencies of DDS are often required, so direct reading can be used more often.