Application of Serial A/D and FPGA in Micro Data Recorder

0 Introduction
In the application field of modern electronic technology, A/D converter is the medium for converting analog signal into digital signal. In data acquisition system, high-precision A/D converter is generally controlled by single-chip microcomputer or other microcontroller. Usually, software simulation of A/D converter timing is adopted, which increases the burden of CPU and reduces the working efficiency of CPU. The high integration and high-speed characteristics of field programmable gate array FPGA make it more suitable for sampling control of high-speed A/D devices than single-chip microcomputer and microcontroller. In addition, in an environment with large electromagnetic interference, the single-chip microcomputer will have the problem of program running away. In the process of using watchdog reset, there will be data loss for the collected data stream. In contrast, the FPGA with trigger edge or level control can collect data more reliably by designing reliable drivers.
This paper takes a 3-channel low-frequency small data recorder as the research background, designs a system with Actel FPGA as the controller, controls the serial output A/D converter ADS8341, and improves the system integration and stability.

1 Introduction to the functions of ADS8341
ADS8341 is a low-power, high-performance 4-channel, 16-bit A/D converter launched by Burr Brown. Its serial interface reduces the cost of system development, and the small package of SSOP-16 is suitable for use in micro devices.
1.1 Functions of ADS8341
CH0~CH3: 4 channels are analog input terminals, which can be set to single-channel input mode or form two groups of differential inputs, CH0-CH1, CH2-CH3.
: The pin is valid at low level, and the A/D converter enters low power mode.
Vref: Reference voltage input terminal.
DCLK: The external clock input terminal of the system, with a maximum input of 2.4 MHz. At this time, the chip A/D conversion speed reaches the maximum value of 100 ksa/s.
: The chip select terminal of the A/D converter, which is valid at low level, and other pins are in high impedance state when the level is high.
DIN: Serial data input terminal. When the chip select signal is valid, the serial data is input into the A/D bit by bit at the rising edge of DCLK.
DOUT: Serial data output terminal. When the chip select signal is valid, the A/D converted digital signal is output bit by bit at the falling edge of DCLK.
BUSY: When the chip select is valid, the A/D converter outputs a high-level signal for one clock cycle.
The Vcc and GND pins are the power supply and digital ground terminals respectively.
1.2 Control word and conversion timing of ADS8341
The control word of ADS8341 is shown in Table 1:

The control word of ADS8341 is 8 bits, S is the start flag, A2, A1, A0 control channel selection, and can provide single channel or differential input mode different channel selection. ***** High level is single channel input mode, PD1, PD0 are power control mode bits, if "11", the power is always in the on mode.

The basic timing of ADS8341 conversion is shown in Figure 1.

As shown in Figure 1, ADS8341 needs 24 DCLK clocks to complete a conversion. At the rising edge of the first 8 clocks, the DIN control word is input. After the control word input is completed, at the rising edge of DCLK, the BUSY signal outputs a high level. At the falling edge of this clock, the converted data is output bit by bit. After a complete conversion, at the rising edge of the 25th clock, DIN can input the high bit of the control word again, ensuring that when the DCLK external clock reaches the highest frequency of 2.4 MHz, the frequency of the A/D converter reaches a maximum of 100 ksa/s.

2 Design of ADS8341 controller based on FPGA
The frequency range of the recorded signal recorded by this recorder system is below 500Hz. In the actual application of the system, the measured signal is oversampled, and the sampling frequency is 5 to 10 times the frequency of the collected signal. The system uses 3-channel fast cycle sampling of the A/D converter, which approximately realizes channel synchronous sampling, which is a quasi-synchronous sampling method. After 72 DCLK cycles, the sequential switching of CH0~CH2 channels is realized. When the A/D converter works at the maximum sampling frequency of 100 ksa/s, the sampling frequency of the recorder system is equivalent to 1/3 of the single-channel frequency. The maximum synchronization error between channel 1 and channel 3 is 48clk, as shown in Figure 2. The minimum error time is about (the sampling frequency is the fastest at this time), which meets the system's requirements for lower frequency signal acquisition.

The system uses Actel's ProASIC3 series A3P100 based on FLASH architecture and uses the Libero integrated development environment. The A/D control module of FPGA mainly includes the following functions:
● Clock controller
The external clock frequency of the recorder system FPGA is 48 MPa. The clock DCLK obtained by dividing the system clock by 20 can provide the maximum working clock of the A/D converter. In addition, through logical control, the clock controller provides several clock frequencies below 2.4 MHz, and the system can choose a lower sampling frequency.
● Unequal duty cycle clock
The clk_div clock signal is introduced into the A/D control module of this system design, with a duty cycle of 2:3, as the control level of din. When the clk_div signal is low, din outputs data, the clk_div signal is high, and din is low.
clk_div support (. duty_factor (duty_factorl), counter_top (counterl)). div_clkl(．reset(clk1_reset), ．clk_in(clk_in1), clk_out(clk_out1)); //Call the clock module with arbitrary duty ratio
●Control word state machine
After the recorder is powered on, the working state is 3 channels cyclic sampling, and the control word state generator generates chO = "1001_1111", ch1 = "101_1111", ch2 = "1010_111 1" cyclically, and converts the control word into serial data and outputs it from the din pin to realize the A/D converter channel switching.

●Control word parallel to serial module
The control words chO, ch1, ch2 need to be converted into serial data and input to AD through din to control channel selection. The cyclic input control word selects 3 channels cyclically. The state control words ch0, ch1, ch2 are transferred to the register. At the falling edge of the DCLK clock, the 7th bit (high bit) is extracted. At this time, the data is relatively stable, and then the register is shifted to the left. It is transferred to AD at the rising edge of the DCLK clock to achieve the control purpose.
●Signal acquisition module
After the A/D converter collects data and inputs it serially into the FPGA, it is converted into parallel data and transmitted to the data bus of the system. According to the basic timing of A/D converter sampling, when the dout pin outputs data serially, the din pin should be kept at a low level. In order to acquire data approximately synchronously for the three sampling channels, after 24 DCLK clock cycles, after the data acquisition, conversion and output of one channel is completed, the acquisition and conversion of the second channel should be entered at the rising edge of the 25th clock of DCLK. Finally, the state cycle timing of the recorder in 72 DCLK clock cycles is the key to A/D module control.

3 Computer simulation analysis and system implementation
The system FPGA uses Actel's chip based on FLASH structure unit, which further reduces the power consumption and size of the system. Actel FPGA's integrated development environment Libero integrates the simulation tool modelsim. Taking the highest sampling frequency of AD as an example, the simulation timing waveform is shown in Figure 4.

In the A/D control module, when "clk_div" is high, data transfer from register "shuru" to register "A" is realized, and when "clk_div" is low, the conversion from parallel data to serial data is realized and output through "din". Figure 4 shows the change of the state of the three control words of the "din" output pin.
The oscilloscope shows the cyclic change of the three groups of control words of the din pin control word serial output, as shown in Figure 5.

4 Conclusion
The system uses FPGA level control to select different channels of multi-channel A/D converters. Compared with single-chip microcomputers, it is more stable and reliable, and the collected data stream is complete. The use of Actel FPGA based on FLASH architecture further reduces the power consumption of the micro data recorder system, while improving the stability of the system in an environment with strong electromagnetic interference.