Application of Embedded Logic Analyzer in FPGA Design

At present, logic analyzers, oscilloscopes and bus analyzers are generally used in the design and verification of ultra-high-density FPGAs. The signals are sent to the instruments through test heads and connectors. Designers must provide enough I/O pins for comprehensive testing and configure enough pins. Add additional logic so that signals can be selected to drive the I/O pins for testing. Although this method can reduce the number of I/O pins required for testing, the steps are cumbersome. In addition, as the complexity of FPGAs increases, most I/O pins use fine-pitch process technology, making it difficult to lead out I/O pins. The method introduced in this article is to insert a logic analysis core into the FPGA design. It has the functions of an ordinary logic analyzer, including triggering, data acquisition and storage. Using the logic analysis core, users can access all signals and nodes inside the FPGA device. Signals from the internal logic circuit can be transferred to the internal memory through the high-speed interconnect in the FPGA. These signals are transmitted at the system clock rate with very little delay.

SignalTap Ⅱ in Altera's Quartus Ⅱ software is such an embedded logic analyzer based on logic analysis core. It meets the requirements of hardware debugging in FPGA development and has the characteristics of non-interference, easy to upgrade, and simple to use.

2 Features and Usage of SignalTap Ⅱ

SignalTap Ⅱ logic analyzer is a second-generation system-level debugging tool that can acquire and display real-time signals of programmable system-on-chip (SOPC), helping designers observe the interaction between hardware and software in their system design. In the programmable logic market, SignalTap Ⅱ logic analyzer is dedicated to Quartus Ⅱ software. Compared with other embedded logic analyzers, it supports the largest number of channels, the largest sampling depth, and the highest clock rate. Quartus Ⅱ software 4.0 and later versions also provide a graphical interface to define specific trigger condition logic to achieve higher accuracy and stronger problem-solving capabilities. SignalTap Ⅱ embedded logic analyzer does not require any external detection or modification of user design files to obtain the status of internal nodes or I/O pins. Currently, the device series supported by SignalTap Ⅱ logic analyzer include: Stratix Ⅱ, Stratix, Stratix GX, Cyclone Ⅱ, Cyclone, APEX Ⅱ, APEX 20KE, APEX 20KC, APEX 20K, Excalibur and Mercury.

There are two ways to embed the SignalTap II logic analyzer in a design: the first method is to create a SignalTap II (.stp) and then define the details of the STP file; the second method is to use the Mega Wizard Plun-In Manager to create and configure the STP file and then use the Mega Wizard to instantiate an HDL output module. Figure 1 shows the process of creating and using the SignalTAP II logic analyzer using these two methods.

Figure 2 shows the SignalTap Ⅱ editing window, which introduces the basic process of setting up SignalTap Ⅱ files.

Set the sampling clock The sampling clock determines the resolution of the displayed signal waveform. The sampling clock collects data at the rising edge. It is recommended to use the global clock instead of the gated clock as the sampling clock.

To set the signal to be tested, you can use the Filter in the Node Finder to find all the SignalTap II nodes for synthesis and layout and routing, and add the signal to be observed. The signals that the logic analyzer cannot test include: the carry signal of the logic unit, the clock output of the PLL, the JTAG pin signal, and the LVDS (low-voltage differential) signal.

Set the sampling depth to store the number of samples required for each signal. The sampling depth ranges from 0 to 128 kB. Set the Buffer acquisition mode. The buffer acquisition mode includes two modes: Circular and Segmented. Whenever the trigger condition is met, a segment of data is captured. This function can remove irrelevant data, making the use of the sampling buffer more flexible.

Trigger Level SignalTap Ⅱ supports multi-level triggering. It can support up to 10 levels of triggering.

The trigger type can be basic or advanced. If basic is selected, the trigger mode must be set for each signal in the STP file. There are 6 trigger modes to choose from in the SignalTap Ⅱ logic analyzer. If advanced is selected, the designer must establish a trigger condition expression for the logic analyzer.

3 Example Analysis

This article takes a sine signal generator as an example to explain the specific process of using an embedded logic analyzer for real-time testing. The design example in this article is based on the EP1C6Q240C8 of the Cyclone series of Altera.

Figure 3 is the structural diagram of the sine signal generator. Its top-level design file is designed in VHDL language, and the design includes two parts: the address signal generator of the ROM, which is served by a 6-bit counter; a sine data ROM, which is constructed by the LPM_ROM module. The bottom layer of LPM_ROM is the EAB, ESB and M4K modules of FPGA. The relationship between the input frequency f0 of the clock CLK of the address generator and the number of waveform data points in each cycle (taking 64 points as an example) and the frequency of the D/A output is: f=f0/64. The RTL circuit diagram corresponding to the sine signal generator designed by the hardware description language is shown in Figure 4.

According to the above steps for using SignalTap Ⅱ, first call in the signal to be tested. Here, select two groups of signals: the 8-bit output bus signal DOUT and the address generation counter internal latch bus Q1 signal. Set the parameters of SignalTap Ⅱ. Select the acquisition clock of the logic analyzer as the main clock signal CLK of the project. Set the sampling depth to 1kB. According to the requirements of the signal to be observed, set the starting trigger position in the sampling depth in the Circulate column of the Buffer acquisition mode box. Finally, select the trigger signal and trigger mode. According to the actual design requirements, select 1 in the Trigger column of the Trigger box; select the check box in front of Trigger and select the trigger signal in the Source column. Select the highest bit Q1[5] of the address counter as the trigger signal. Select the rising edge trigger mode in the Pattern column.

After the external experimental development system is connected, compile and download, click the Autorun Analysis button on the SignalTap Ⅱ panel to start SignalTap Ⅱ for sampling and analysis. At this time, you can observe the real-time signal from the FPGA inside the experimental board through the JTAG port from the SignalTap Ⅱ data window. The output signal of this example is shown in Figure 5.

4 Conclusion

Through the above examples, it is not difficult to find that using Altera's SignalTap Ⅱ embedded logic analyzer for chip testing provides a good way to greatly reduce design costs and speed up the design cycle. Users can analyze and judge system faults by capturing all signals and nodes inside the FPGA device without external dedicated instruments. It should be noted that SignalTap Ⅱ embedded logic analysis needs to work in JTAG mode. After debugging is completed, SignalTap Ⅱ needs to be removed from the design to avoid wasting resources. It can be foreseen that SignalTap Ⅱ embedded logic analyzer will be widely used in FPGA design.