Explanation of test technology in high-speed PCB interconnect design

Interconnect design technology includes testing, simulation, and various related standards, among which testing is the method and means to verify various simulation analysis results. Excellent testing methods and means are necessary conditions to ensure interconnect design analysis. For traditional signal waveform testing, the main focus should be on the length of the probe lead to avoid unnecessary noise introduced by the pigtail. This article mainly discusses the new application and development of interconnect test technology.

Figure 1: 0.1uf capacitor impedance curve

In recent years, with the continuous increase in signal rates, the test objects have undergone significant changes. They are no longer limited to the traditional use of oscilloscopes to test signal waveforms. Power supply noise, synchronous switching noise (SSN), and jitter have gradually become the focus of attention of interconnect design engineers. Some instruments in the RF field have been applied to interconnect design. Commonly used test instruments in interconnect design include spectrum analyzers, network analyzers, oscilloscopes, and various probes and fixtures used by these instruments. In order to adapt to the ever-increasing signal rates, the use of these test instruments has changed significantly. This article uses these test instruments as tools to introduce the development of interconnect design test technology in recent years, mainly from the aspects of test calibration methods, passive device modeling methods, power integrity testing, and clock signal jitter testing methods.

At the end of the article, the development of future testing technology will be briefly introduced in conjunction with the just concluded designcon2005 conference.

Calibration Method

Among the three commonly used test instruments, the calibration method of the network analyzer is the most rigorous, followed by the spectrum analyzer, and the calibration method of the oscilloscope is the simplest. Therefore, we mainly discuss the calibration method of the network analyzer here. There are three commonly used calibration methods for network analyzers, thru, trl and solt. The characteristics of the three methods are shown in Table 1.

Table 1: Common calibrations for network analyzers

The essence of thru is normalization. During calibration, the network analyzer records the test result of the fixture (s21_c). In actual testing, the test result (s21_m) is directly divided by s21_c to obtain the test result of the device under test (s21_a). Thru calibration ignores the reflection caused by the mismatch in the test fixture and the electromagnetic coupling in space. Therefore, its calibration accuracy is the lowest. This calibration method can be used when only s21 is tested and the test accuracy requirement is not high.

In non-coaxial structures such as PCB, it is sometimes necessary to test the characteristics of traces, vias, connectors, etc. In this case, the test instrument supplier does not provide standard calibration parts, and it is difficult for testers to make good open circuit, short circuit, matched load and other calibration parts at the test calibration port. Therefore, traditional solt calibration cannot be performed. The advantage of using trl calibration is that no standard calibration parts are required, and the test calibration port can be extended to the required position. At present, trl calibration is widely used in PCB structure testing.

Solt is generally considered to be the standard calibration method. There are 12 calibration error parameters in the calibration model. Various errors are calibrated and calculated by using short circuit, open circuit, load and through circuit. Since test instrument suppliers usually only provide coaxial calibration parts, the Solt calibration method cannot be used in non-coaxial structures.

The above three calibration methods can be analyzed in detail using signal flow graphs, where each error parameter has a corresponding parameter in the signal flow graph. Through the signal flow graph, we can clearly understand the error sensitivity of various calibration methods, so as to understand the error range of the actual test. One point that needs to be pointed out here is that even the standard solt calibration method ignores five error parameters in the calibration model. Normally, these five error parameters will not affect the calibration accuracy. However, if you do not pay attention to the design of the calibration fixture when using it, it will be impossible to calibrate.

The spectrum analyzer provides a standard source for calibration. When calibrating, you only need to connect the internal standard source to the input port through the test fixture. The calibration takes about 10 minutes. The calibration of the oscilloscope is even simpler. Just connect the probe to the internal standard source and confirm. The calibration takes about 1 minute. < Testing and modeling of passive components

As signal rates continue to increase, passive components play an increasingly important role in signal links. The accuracy of system performance simulation analysis often depends on the accuracy of passive component models. Therefore, testing and modeling of passive components have gradually become an important part of interconnect design for various equipment suppliers. Commonly used passive components include: connectors, PCB traces and vias, capacitors, and inductors (ferrite beads).

In high-speed signal integrity design, connectors have the greatest impact on signal links. For frequently used high-speed connectors, the usual practice is to make calibration fixtures according to the TRL calibration method and test model the connectors for simulation analysis. The test modeling method for PCB traces and vias is similar to that for connectors. TRL calibration is also used to move the test port to the desired position, and then test modeling is performed.

Figure 2: Impedance characteristics of a single board power supply

Capacitor models are used in signal integrity analysis, and more importantly in power integrity analysis. The commonly used capacitor modeling instruments in the industry are impedance analyzers and network analyzers, which are suitable for different frequency bands. Impedance analyzers are suitable for low frequency bands, and network analyzers are suitable for high frequency bands. If a network analyzer is used for power integrity testing in actual tests, it is recommended to use a network analyzer in the entire frequency band of capacitor modeling to ensure consistency in modeling and application. Since the impedance of the capacitor is small, a parallel method is usually used when using a network analyzer for modeling. At present, the problem that the industry has not solved in capacitor modeling is how to eliminate the mutual coupling between the fixture and the capacitor to reduce the impact of the fixture on the modeling results.

In traditional power supply design, inductors (magnetic beads) are often used to isolate the power supply to reduce noise interference. In actual design, it is often the case that the power supply ground noise is reduced by removing the isolation inductor (magnetic bead). This is because the inductor (magnetic bead) resonates with other filter components. In order to avoid this situation, it is necessary to model and simulate the inductor (magnetic bead) to avoid resonance. The commonly used inductor (magnetic bead) modeling method in the industry also uses a network analyzer. The specific method is similar to capacitor modeling, except that the inductor (magnetic bead) modeling uses a series method, while the capacitor modeling uses a parallel method.

The modeling of the above passive components is mainly used in signal integrity and power integrity. In recent years, EMI simulation analysis is gradually developing, and the test modeling of EMI passive components has gradually become the focus of interconnect design. Figure 1 shows the impedance curve of the capacitor.

Power integrity testing

As chip power continues to increase and operating voltage continues to decrease, power ground noise has gradually become a focus of attention in interconnect design. From the perspective of the test object, power integrity testing can be divided into two parts: power system characteristics testing and power ground noise testing. The former is a test of the performance of the system power supply part (passive test), and the latter is a direct test of the power ground noise when the system is working (active test). Synchronous switching noise can also be classified as power ground noise.

When testing the performance of a power system, a network analyzer is usually used, and the test object is the self-impedance and transfer-impedance of the power system. In general, the impedance of the power system is much smaller than the impedance of the network analyzer system (50 ohms), so when testing, only a through calibration is required, and the impedance of the power system can be obtained using the formula s21=z/25. Figure 2 shows the impedance characteristics of a single-board power supply.

To test the power supply ground noise, you can use a spectrum analyzer and an oscilloscope. The input port of the spectrum analyzer cannot be connected to the DC component, so when testing the power supply ground noise, you must connect DC-blocking in series in the test fixture. The input impedance of the spectrum analyzer is 50 ohms, and the impedance of the power supply ground network is generally in the milliohm level, so the test fixture will not affect the system under test. The input impedance of the oscilloscope changes with different settings. Taking the Tektronix TDS784 as an example, its low-frequency cutoff frequency changes with the coupling mode and system impedance, as shown in Table 2.

The methods described above are all for testing the power ground noise on the single board, but what really affects the chip operation is the power ground noise inside the chip. At this time, it is necessary to use the synchronous switching noise test to determine the power ground noise inside the chip. Assume that the chip has n IO ports, keep one of them static, and flip the other n-1 at the same time, and test the signal waveform on the static network, that is, synchronous switching noise. Synchronous switching noise includes both power ground noise and crosstalk between different signals in the package. There is currently no way to completely distinguish the two.

Table 2: Oscilloscope input impedance changes with settings

In some high-end products, jitter has gradually become an important indicator that affects product performance. Here we only briefly introduce how to use a spectrum analyzer to test clock signal jitter and locate problems. The jitter test of data signals is not involved for the time being.

In most systems, the clock is generated by a crystal oscillator or a phase-locked loop. The jitter test of the clock signal is relatively simple and does not require high-end test instruments. A common spectrum analyzer can be used to locate the problem. The spectrum of an ideal clock signal is a clean discrete spectrum with components only at multiples of the clock frequency. If the clock signal jitters, side lobes will appear near these multiples, and the jitter size is proportional to the power of these side lobes.

The specific method of using a spectrum analyzer to test clock jitter is to find any testable point on the clock signal link, connect the signal at that point to the spectrum analyzer through dc-blocking, and observe the test results. Since the test fixture is a linear system, there is no need to worry about the generation of new spectrum components. As mentioned earlier, the clock is generated by a crystal oscillator or a phase-locked loop. In this case, the important reason for introducing clock jitter is the power supply noise of the crystal oscillator or the phase-locked loop. By comparing the power supply noise of the crystal oscillator or the phase-locked loop obtained by the method described above with the side lobes in the clock spectrum, the cause of the clock jitter can be basically determined. The solution to the problem is to redesign the filter circuit of the crystal oscillator or the phase-locked loop based on the side lobes of the clock spectrum. In general, these problems can be solved by reasonably selecting filter capacitors.

Technical direction of designcon2005

Designcon is the first annual conference in the field of interconnect technology. At this year's Designcon2005, the following technology trends were highlighted:

a. Pure power integrity simulation and testing has been widely used in the industry and is no longer a difficult point in analysis work.

b. The modeling of capacitors and inductors (magnetic beads) has been promoted in the industry, and the methods are relatively complete.

c. The focus of interconnect design has shifted to packaging. Board-level analysis has become more mature, and the simulation and testing of synchronous switching noise has gradually become a concern in the industry.

d. Jitter testing methods and standards have gradually become a concern in the industry. At the conference, many test equipment suppliers launched their own jitter analyzers.

Summarize

This article briefly introduces the test objects and test methods in the current interconnect design field. With the continuous increase in signal rates, some new test contents have gradually emerged, including power supply ground noise, passive device modeling, jitter, etc. Based on his own work experience, the author proposed test methods for these new test contents. In traditional signal waveform testing, the main consideration should be to reduce the length of the ground wire to avoid pigtail coupling into noise and reduce test accuracy. In future interconnect designs, due to the increase in signal operating frequency, the focus of work will shift to chip packaging, and related testing and modeling technologies will become the focus of work.