What is the significance of China Microelectronics' breakthrough in FinFET technology?

IoT Technology Review: SOI technology is a full dielectric isolation technology that can be used to replace silicon substrates. Why has FinFET become mainstream? Even GlobalFoundries, which has mastered the 22nm FD-SOI process, still purchased Samsung's 14nm FinFET technology license? This article will analyze: What is the impact of the new FinFET logic device process breakthrough?

Recently, the China Institute of Microelectronics Integrated Circuit Pilot Process Research Center has made important progress in the research of the next generation of new FinFET logic device technology. The research group of Yin Huaxiang, a researcher at the Institute of Microelectronics, has realized full metallization of source and drain (MSD) on the new FOI FinFET using low-temperature and low-resistance NiPt silicide, which can significantly reduce the source-drain parasitic resistance, thereby improving the performance of N/PMOS devices by about 30 times, and making the driving performance reach the international advanced level.

The paper based on this research result was accepted by the 2016 IEEE International Electron Devices Meeting (IEDM), and Zhang Qingzhu gave an academic report at one of the key sessions of IEDM - Silicon-based Pioneer CMOS Process and Manufacturing Technology (PMT).

So, what is this new FinFET logic device process used for? In layman's terms, it is the next process used to manufacture logic devices such as CPUs. For example, most of the current 14/16nm chips use FinFET technology, and this new FinFET is a useful exploration of the next generation of technology in China.

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FinFET and SOI

Before introducing the new processes developed by microelectronics, let’s first introduce FinFET and FD-SOI processes.

Fin in FinFET refers to fin type, and FET refers to field effect transistor, which together is fin field effect transistor. Before the advent of FinFET, MOSFET has been used, but when the gate length is less than 20nm, the source and drain are too close and the oxide is thinner, which is likely to cause leakage.

Therefore, three professors from the University of California, Berkeley, namely, Hu Zhengming, Tsu-Jae King-Liu, and Jeffrey Bokor, invented FinFET, which changed the original 2D MOSFET into 3D FinFET. Since the structure is very similar to a fish fin, it is named "fin-type".

In 2015, Professor Hu Zhengming won the US National Technology and Innovation Award for his contribution to FinFET. According to Professor Hu Zhengming himself, FinFET has achieved two breakthroughs: one is to make the crystal thinner and solve the leakage problem, and the other is to develop upward, changing the internal structure of the chip from horizontal to vertical, that is, changing the 2D MOSFET to a 3D FinFET.

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What effect does this approach have?

TSMC once said: The 16nm FinFET process can significantly improve chip performance, power consumption, and reduce leakage rate. The gate density is twice that of TSMC's 28nm HPM process. The speed can be increased by more than 40% at the same power consumption, and the power consumption can be reduced by more than 60% at the same frequency.

It is worth mentioning that the doctoral thesis supervisor of Liang Mengsong, the former TSMC employee who was poached by Samsung, was Hu Zhengming. This is probably one of the reasons why Samsung was able to achieve a great leap forward in 14nm FinFET.

Compared with FinFET, which focuses on transistors, SOI technology focuses on the wafer substrate.

SOI (Silicon-On-Insulator) refers to silicon on an insulating layer, and is a new type of raw material used by integrated circuit suppliers. As a full dielectric isolation technology, SOI technology can be used to replace silicon substrates. FD-SOI is to make a difference on the substrate. Under the same transistor conditions, the use of FD-SOI technology can achieve a 30% performance improvement at the same power consumption, or a 30% reduction in power consumption at the same performance.

According to data released by GlobalFoundries:

The 22nm FD-SOI process consumes 70% less power than the 28nm HKMG process.

The chip area is 20% smaller than 28nm Bulk;

The number of photolithography layers is reduced by nearly 50% compared to the FinFET process;

The chip cost is 20% lower than 16/14nm.

If the data released by GlobalFoundries is true, then 22nm FD-SOI has performance and power consumption comparable to 14/16nm FinFET, but the cost of the chip is comparable to 28nm. In addition, GlobalFoundries also stated that if the process is upgraded to 14nm, the performance will be improved by 35% compared to 28nm SOI, and the power consumption will be reduced to half of the original.

In addition, SOI also has higher transconductance, reduced parasitic capacitance, weakened short channel effect, steeper subthreshold slope, and the radiation resistance of SOI circuits is 100 times higher than that of bulk silicon circuits. In high temperature environments, SOI devices perform significantly better than bulk silicon devices.

So, why did FinFET become mainstream, even though GlobalFoundries, which has mastered the 22nm FD-SOI process, still purchased Samsung's 14nm FinFET technology license?

The reason is that the cost of using SOI process is relatively high, and at present Intel and TSMC can make chips that meet the requirements on silicon substrates, so silicon substrates are still used. TSMC has a huge market share, and Intel has the best technology. The two companies chose FinFET, and naturally the entire industry chain followed. SOI process can only find a presence in the RF and sensor markets.

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The slowdown of Moore's Law is an opportunity for the Institute of Microelectronics to develop its own process

Due to technical and commercial reasons, Moore's Law has lost its effectiveness, and is constrained by factors such as lithography technology and the limitations of silicon materials. If chip performance is to be further improved, combining FinFET and SOI is a solution - using FinFET+SOI substrate to improve chip performance. After all, FinFET (transistor) + FD-SOI (substrate) is obviously better than FinFET (transistor) + silicon substrate.

Moreover, due to commercial reasons, when the process is greater than 28nm, the cost will gradually decrease as the chip process is improved. However, after the chip process reaches 28nm, the cost of a single transistor will increase instead of decrease. This makes the X nm FinFET (transistor) + FD-SOI (substrate) approach not only not inferior to the Y nm FinFET (transistor) + silicon substrate (X>Y) in performance, but is also likely to have certain advantages in business. This is also the reason why SOI-like devices (FOI FinFET) that are compatible with the mainstream fluid silicon FinFET process and form dielectric isolation through a bulk silicon substrate have become an important research direction.

The new process of the Institute of Microelectronics is similar to the idea of ​​FinFET (transistor) + FD-SOI (substrate). According to the official introduction of the Institute of Microelectronics, the new FinFET device process has the following characteristics:

First, in view of the inherent defects of FOI FinFET, the use of fully metallized source and drain based on low-temperature and low-resistance NiPt silicide on dielectric isolation can effectively eliminate the leakage effect on the conventional body fin and significantly reduce the source and drain parasitic resistance. The source and drain contact resistance and sheet resistance of FOI FinFET with an actual physical gate length of 20nm are reduced by 10 times and 1.1 times respectively, thereby improving the performance of N/P type FOI FinFET devices by about 30 times and maintaining the excellent short channel suppression characteristics of the new structure.

Secondly, the lattice mismatch between the NiPt all-metal source and drain and the Si interface generates additional tensile stress in the channel, which effectively enhances the electron mobility and provides a new integration solution for the channel mobility enhancement technology of N-type FOI FinFET.

Third, the source-drain parasitic resistance is further reduced through Schottky source-drain (SBSD) technology, effectively improving the driving performance of P-type FOI FinFET devices (greater than 50%). The research results show that the fully metallized source-drain FOI FinFET has an order of magnitude lower leakage than conventional FinFETs with similar processes, a 2-fold increase in driving current, and driving performance at low power supply voltages that reaches the international advanced level. Since it replaces the traditional source-drain SiGe epitaxial technology, it has better compatibility with large-scale FinFET devices with extremely small pitch, helps reduce manufacturing costs, and improves yield, and has high technical value.

It is for this reason that the new FinFET device process of the Institute of Microelectronics has been favored by internationally renowned mainstream integrated circuit companies such as IBM and STMicroelectronics.

Finally, whether it can be commercialized depends on technical indicators, but industry alliances are also very important. If domestic research institutes and enterprises can form an industry alliance with IBM, STMicroelectronics, GlobalFoundries and other companies to jointly promote this technology, they may be able to achieve some results.