Intel Research Vice President Song Jiqiang: Moore's Law is a banner of innovation and is still continuing

Editor's note: Moore's Law was proposed by Gordon Moore, one of the founders of Intel. Its core content is that the number of transistors that can be accommodated on an integrated circuit will double approximately every 18 months. For decades, Intel has been the most staunch defender of Moore's Law and has closely followed the development of Moore's Law. However, as the density of transistors in chips increases, the continuation of Moore's Law has become increasingly difficult, which has become a common problem faced by the industry.

作者丨沈丛

Editor: Zhang Xinyi

Art Editor: Maria

Producer: Lian Xiaodong

Recently, Hu Chunmin, editor-in-chief of China Electronics News, interviewed Song Jiqiang, vice president of Intel Research Institute and director of Intel China Research Institute, and had an in-depth discussion on this issue.

Interviewer:

Song Jiqiang, Vice President of Intel Research and Director of Intel China Research Institute

Hu Chunmin: Some people say that Moore's Law has reached its limit. If we want to continue Moore's Law, we need more disruptive technological innovation and breakthroughs. What suggestions does Intel have for continuing Moore's Law?

Song Ji Qiang : Moore's Law is not only a physical law, but also a prediction of the future technology and economic development of semiconductors. In terms of expression, it refers to the density of semiconductor transistors within a certain size, which is improved in various ways. At the same time, it has another characteristic, that is, after the performance of semiconductors reaches the average level, the price of semiconductors will also decrease in an exponential manner. Therefore, from a holistic perspective, Moore's Law actually promotes the cost-effectiveness of semiconductor products by predicting the exponential improvement of semiconductors.

The development of Moore's Law (Image source: Intel Corporation)

From this, we can see that Moore's Law is not a technical law or a physical rule, but a bold prediction of the direction of industrial development by experts in the semiconductor field, and they regard it as a belief. Of course, belief alone is not enough, we must also execute and promote its development, and promote the implementation of technologies related to Moore's Law through actual technological progress and improvement of production processes.

For decades, Intel has been the originator, guardian and promoter of Moore's Law. In the past two decades, Moore's Law has been rumored to stagnate or even end many times. But in fact, every time there is such a difficulty, it means that the development of semiconductor technology has encountered huge technical challenges, resulting in the lack of suitable semiconductor technology in the short term to promote Moore's Law to develop at its original pace. But every time everyone thinks that Moore's Law is about to fail, some new technologies will always appear and be applied to the development of the industry to push Moore's Law forward. For example, the emergence of metal gate technology with high-K (dielectric constant) dielectrics in 2008 broke through the chip's stuck point in the 32nm process. In addition, the emergence of 3D FinFET architecture has helped chip manufacturing successfully break through the 28nm process.

Intel's transistor innovation milestones (Image source: Intel Corporation)

However, as chip manufacturing processes move to 5nm and 3nm, the design of many process structures has begun to approach the atomic level, which places high demands on design accuracy and yield, making technological breakthroughs more difficult. Therefore, today's chip miniaturization will rely more on lithography technology and new architectural design methods.

First of all, in terms of lithography technology, the accuracy of the lithography machine needs to be greatly improved so that it can lithography chips of smaller sizes. Secondly, if you want to effectively improve chip performance while reducing chip size, you need a new architecture design method. Today, the industry believes that the new GAA (Gate All Around) architecture design method can effectively improve the performance of advanced process chips. Intel designed the RibbonFET architecture based on GAA. After Intel's chip process enters angstroms (such as Intel's 20A process), the RibbonFET architecture will be adopted.

For the semiconductor industry, Moore's Law is like a banner. If you follow it, you can use various innovations to reach the corresponding technical level. In addition, the development of Moore's Law cannot be achieved by one's own efforts, but requires the joint efforts of the upstream and downstream of the industry chain. If everyone believes that Moore's Law can continue to develop, then it can still continue at a certain rhythm.

Hu Chunmin: The continuation of Moore's Law is usually based on the advancement of process technology. Some foundry companies in the industry have achieved mass production of 5nm and 4nm and are moving towards smaller processes. What are the differences between Intel and other manufacturers in process technology? Why do you insist on this route?

Song Jiqiang: Since the late 1990s, different manufacturers have no longer unified their naming methods for process nodes. Previously, because people could measure the length of the transistor gate more accurately, companies often used the length of the transistor gate as the name of a certain generation of chip process. However, after the progress of chip miniaturization slowed down, the reduction in transistor gate length was not as obvious as before, but people still hoped to reflect the continuation of Moore's Law in the naming of chip processes. Therefore, after entering the 21st century, the naming rules of various manufacturers became inconsistent. Some manufacturers still use gate length to name, while others use other feature sizes to name, thereby emphasizing their ability to make the process smaller.

Therefore, the numerical value of chip manufacturing process is no longer of much reference significance for today's semiconductor manufacturing process. In terms of measuring chip performance, other numerical values ​​are also of reference significance. For example, the condition of transistors in a chip is also an important indicator of chip performance, that is, what density the transistors can achieve. These technical levels are even more convincing than the nanometer value.

It can be seen that if you want to measure the advancement of semiconductor process technology, you need to combine many indicators for comprehensive evaluation, rather than just generalizing by the value of a few nanometers. For Intel, it has always adhered to strict requirements and steady progress in promoting process technology, and has not blindly pursued speed. For example, Intel's 14nm, 14nm+, 14nm++, 10nm, 10nm+ and other process technologies, in fact, each plus sign represents a process improvement, some are 10% improvement, and some are 20% improvement. Sometimes friendly companies will directly release this improvement as a new process node, but Intel does not.

Intel's latest process roadmap (Image source: Intel Corporation)

Intel encountered some difficulties in the process of advancing from 14nm to 10nm, and was a little slower than its competitors. Currently, Intel is about one to one and a half years behind its competitors in the most advanced process nodes. Therefore, Intel proposed a new strategy of IDM 2.0, with the goal of advancing five process nodes within four years. Under this strategy, when Intel advances to Intel 20A, the process technology will probably be on par with the top level in the industry, or even slightly stronger. By Intel 18A, Intel will be able to return to the leading position in the industry in terms of process technology. And this is not groundless, it is measured by various precise indicators.

Hu Chunmin: The numerical difference between Intel 18A and Intel 20A seems very small. What kind of technical optimization and progress will there be between the two?

Song Jiqiang: The gap between the two is mainly reflected in the performance improvement of the RibbonFET architecture. This architecture will officially appear when Intel 20A comes out, and will become more perfect when Intel 18A comes out, thereby further optimizing chip performance. It will optimize the power supply method, switching speed control, power consumption, etc., and will continue to improve in subsequent processes.

The development process of advanced process chips involves thousands of steps, and it is not easy to mass-produce chips with a very high yield. Architectural design is difficult to achieve in one step and requires continuous optimization and upgrading. Transistors can be regarded as pieces of Lego, and each small piece can create different architectural products. Some architectures can create high-performance computing, while some architectures can achieve lower power consumption while focusing on performance. At the same time, different performance requirements also have different requirements for transistor testing scenarios. During the construction process, the architecture needs to be continuously tested to promote the continuous optimization of the architecture and achieve continuous technological progress.

Hu Chunmin: Nowadays, some foundries have turned to GAA architecture to promote the research and development of more advanced processes. How is Intel different from other companies in terms of architectural innovation breakthroughs?

Song Jiqiang : GAA is a transistor construction method, which uses a gate to wrap around the trench fins on both sides. This is a universal architecture, but each company has different designs for specific transistor structures.

Intel's new RibbonFET transistor (Image source: Intel Corporation)

Intel has implemented an innovative architecture, RibbonFET, on GAA transistors. The RibbonFET architecture allows a gate to simultaneously wrap around multiple grooves for current conduction. At the same time, the design of the trench fins can be widened or narrowed according to different needs, making the entire design relatively flexible. Multiple fins can be completely wrapped by a gate, while increasing the size without taking up too much plane size. While widening the fins, it can also ensure that the current passing through is large enough without increasing the size of the overall structure. This is also the uniqueness of Intel's architectural design.

Today, the entire industry is optimistic about the GAA structure and has begun to use it in the structural design of transistors, but the most critical issue is whether the chip can be mass-produced, which now seems very difficult.

Hu Chunmin: Packaging was once considered a relatively low-tech link in the field of integrated circuits. Now the industry has proposed the concept of advanced packaging, including technologies such as 3D stacking, and regards it as the key to promoting the development of Moore's Law. How does advanced packaging technology promote the development of Moore's Law? What breakthroughs has Intel made in this regard?

Song Jiqiang: Advanced packaging will become an important technical direction to continue Moore's Law. Previously, people usually focused on the design of transistors in chips and worked on how to make separate dies (independent functional chips), including how to optimize the structure and improve power supply. In terms of packaging, the bandwidth, power consumption and connection spacing of traditional packaging outside the die vary greatly, resulting in the inability to integrate dies in the same chip system and difficulty in improving chip performance.

Intel's innovative packaging technology milestones (Image source: Intel Corporation)

Therefore, it is difficult to effectively improve chip performance only through traditional packaging methods, but this series of problems have been effectively solved in advanced packaging. For example, the use of advanced hybrid bonding technology can reduce the pitch size in the package to less than 10 microns. Therefore, by using advanced packaging technology, the difference in feature size in the chip can be greatly reduced, and the resistance of the connection between each other and the power consumption of the connection length will also decrease accordingly, which can achieve the effect of joint optimization, thereby effectively improving chip performance.

In advanced packaging, in addition to planar packaging, 3D packaging can also be used to improve chip performance. 3D packaging seals computing units together, greatly increasing chip density.

The emergence of 3D packaging technology means that the chip will no longer occupy more space in the plane direction, but will extend upward through vertical stacking. Although the effect will be better, the technical difficulty will also increase. First, the signal transmission speed between the wires will become faster; second, the power consumption of the operator will also increase. Therefore, in the field of 3D packaging, the improvement of functional density and the reduction of power consumption are the directions that need to be optimized in the future.

Foveros is a 3D packaging technology launched by Intel, including the already launched Foveros omni and Foveros direct technologies. These technologies effectively connect computing units in the vertical direction, can smoothly supply power, and do not require drilling holes on the chip and die, thus saving precious plane resources.

Hu Chunmin: In terms of advanced packaging, what kind of cooperation have large companies carried out on heterogeneous integration, chiplet and other technologies?

Song Jiqiang: When advanced packaging is integrated in 2D, each chip or core can be interconnected in a mainstream way, but in 2.5D and 3D heterogeneous integration, it becomes relatively difficult to connect in a mainstream way, and a unified interconnection standard is needed. Therefore, Intel launched the UCIe (Universal Core Interconnect Technology) Alliance, aiming to develop a unified and public interconnection standard. The UCIe Alliance includes chip design manufacturers, packaging and testing manufacturers and other manufacturers in various links of the semiconductor industry chain, so that each industry chain forms an interconnected relationship, which is conducive to the formulation of standards.

The establishment of the UCIe Alliance not only enables Intel to share technology and interfaces with other manufacturers, but also effectively promotes upstream and downstream partners in the industrial chain to jointly form better industrial interconnection technology and promote industrial development.

Hu Chunmin: How can Chinese companies better participate in the field of heterogeneous integration technology?

Song Jiqiang: Nowadays, Chinese companies are actively participating in the development of heterogeneous integration technology. There are already several Chinese companies in the UCIe alliance. Heterogeneous integration is also one of the technical fields that the Chinese semiconductor industry focuses on researching, and all aspects of industry, academia and research attach great importance to it. For example, Liu Ming, an academician of the Chinese Academy of Sciences, mentioned hybrid bonding technology last year; Wei Shaojun, a professor at Tsinghua University and an academician of the International Eurasian Academy of Sciences, also specifically mentioned heterogeneous integration at a conference in March this year, and said that micro-nano system integration represented by three-dimensional hybrid bonding technology will be the main means for semiconductors to continue Moore's Law in the future. Since there is still a large technological gap between the traditional packaging field and the advanced packaging field, if China wants to better develop heterogeneous integration technology, it needs to combine the capabilities of academia and industry to jointly promote development.

Hu Chunmin: What role can heterogeneous computing play in the continuation of Moore's Law?

Song Jiqiang: Nowadays, people are paying more attention to heterogeneous computing technology because heterogeneous computing can optimize chip performance based on the existing chip process, without reducing the chip process, but only through the design innovation of computing architecture. In future chip designs, there will be traditional scalar computing architectures, vector architectures, and even matrix computing architectures. After integrating these architectures, the underlying chip resources can be more effectively utilized, and more efficient computing capabilities can be exerted, thereby effectively improving chip performance.

Intel's new x86 core architecture: energy efficiency core, performance core (Image source: Intel Corporation)

With the acceleration of digital transformation, the demand for computing power in all walks of life is increasing. It is far from enough to use only conventional chip architecture to process this data. By adopting a combination of multiple architectures, it is possible to match the appropriate architecture for data processing according to different functions, making work more efficient. Intel CPU uses heterogeneous computing technology. The chip contains both energy-efficient core E-core (Efficient Core) and performance core P-core (Performance Core), taking into account the energy efficiency and performance of the chip. While improving chip performance, it can also be flexibly adjusted according to customer needs.

Hu Chunmin: Wide bandgap semiconductor technology has been hotly discussed recently, and some carbon-based power devices have begun to be used in automobiles. Will carbon-based semiconductors replace silicon-based semiconductors in the future?

Song Jiqiang: Compared with traditional silicon-based semiconductors, wide bandgap semiconductors have advantages in the application of some power devices, but it does not mean that they can replace silicon-based semiconductors, because the application field of wide bandgap semiconductors is still very limited, far less than that of silicon-based semiconductors. For example, wide bandgap semiconductors are not suitable for use as computing components and cannot be used in the CPU field. Wide bandgap semiconductors are another technical direction, not a replacement technology for silicon materials.

Hu Chunmin: Intel CEO Pat Gelsinger said that the four major technological superpowers of today are ubiquitous computing, cloud-to-edge infrastructure, ubiquitous connectivity, and artificial intelligence. These four technologies will be of great help to the future Internet of Everything and digital development. What plans does Intel have for this?

Song Jiqiang: These four major technical forces are regarded by Intel as the four super powers of digital transformation, and are also the technical fields that Intel focuses on. Ubiquitous computing means that the future Internet of Everything technology will become more intelligent, so that future computing will no longer be limited to the connection of mobile phones, computers and other devices, but will be able to connect more devices. This also means that common devices in the future, whether implanted or connected, will need to be equipped with computing capabilities. For example, the table in the conference room can also have the capabilities of touch, interaction, recording, etc.; the wall can even automatically become a projection or interactive scene.

Ubiquitous computing power may exist in only one independent device or in multiple connected devices, but the demand for communication technology is very high. During the communication process, the device needs to obtain data from other devices or obtain some additional computing resources. Therefore, for communication equipment, all-round connection is required, including one-stop connection between the front end and the back end - such as low-latency and high-throughput connections provided by 5G and Wi-Fi, as well as some wired connections, such as the connection between the operator's access network and the backbone network.

It can be seen that ubiquitous computing power also requires ubiquitous connectivity. To achieve ubiquitous connectivity, Intel is committed to communication technology innovation, including 4G, 5G and even 6G network standardization and customization technology. In the system of operators and service providers, Intel has FlexRan software technology as support. In hardware technology, Intel can provide support for network acceleration technologies such as smart network cards and IPUs.

In the infrastructure from cloud to edge, in addition to powerful hardware support, highly interoperable software is also required to make the hardware effective and coordinate and schedule hardware resources. Therefore, Intel provides different types of development kits at the software level to provide a more comprehensive software stack.

Heterogeneous computing is a key technology in the infrastructure from cloud to edge. However, the scheduling of heterogeneous computing units has become a new challenge. How to achieve the effect of reducing costs and increasing efficiency while fully scheduling heterogeneous computing units requires collaborative exploration in the industry. Therefore, Intel and its partners launched the oneAPI plan to provide a unified programming framework for heterogeneous computing, covering edge computing from cloud to end, so that developers can flexibly schedule computing resources.

Today, the amount of data is increasing exponentially, and it is difficult to process it with human power alone. Therefore, artificial intelligence technology has become one of the four super powers. In the future, in addition to the data generated by the digital system itself, there will be data reflected from the physical world to the digital field, including but not limited to human daily vision, voice and other data. These massive amounts of data require AI algorithms to process and optimize them to connect with hardware. Only by effectively integrating data and maintaining verticality can artificial intelligence truly play its high efficiency advantages and improve productivity.

Hu Chunmin: Previously, in the development of Moore's Law, there were always some characteristic laws that allowed people to accurately predict the cost, performance and other indicators of the next generation of chips according to these laws. In the post-Moore era, will the performance iteration and cost expectations of chips still follow the same laws?

Song Jiqiang: The rules will still exist, but they will not be long-term stable rules. This is because the technical difficulties were not high before, and the regularity was relatively stable during the chip iteration process, and people were able to predict the development of chip technology long in advance. However, as the technical difficulty becomes greater and the uncertainty factors increase, it is difficult for people to predict the relevant situation of the next generation of chip technology long in advance. Often, accurate information can only be obtained when the technology is about to be launched.

For example, Intel's Intel 18A chip, the relevant technical details are still unknown, and we need to wait until 2023 when Intel 20A is about to be released and the chip process officially enters the angstrom to know the specific situation. The development of Intel 18A chips requires more than 2,000 process steps, and it is difficult to determine what variables will appear in this process. Therefore, although the regularity is not as strong as before, it still exists.

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