[MCU Knowledge Base] How to use the I2C Slave peripheral of the EFM8 8-bit MCU

When developing products, users of Silicon Labs' EFM8 8-bit MCU series need to know more about how to use the EFM8LB1 / EFM8BB3 I2C slave device to make it look completely different from the SMBus peripherals? In response, we have created a knowledge base article to guide engineers to speed up the design process. Welcome to read below or click " Read the original text " to read the full article in the Silicon Labs Chinese community.

The M8LB1/BB3 includes an I2CSLAVE peripheral, which includes many features that facilitate high-speed transmission, but may confuse users familiar with traditional SMBus operations. Here, we briefly introduce the I2CSLAVE device and attach the I2C SLAVE device bootloader example code for reference. This code example is written for EFM8BB3, but can be easily ported to EFM8LB1 if necessary.

The I2C peripheral contains a 2-byte FIFO and a 1-byte shift register for TX/RX respectively. The I2C SLAVE device supports automatic ACK/NACK of the I2C master device, which is controlled by the BUSY bit of the I2C0CN0 register. By default, BUSY is "1" and the device does not respond to the I2Cmaster device. All I2C data sent to the device will be NACKed. We should set this BUSYbit to "0" and the device will acknowledge the I2Cmaster device. The master device keeps sending data to the device, and the device automatically acknowledges up to 3 ACKs to the master device because there are two bytes in the FIFO and 1 byte in the shift register. Then SCL remains low to indicate that the device cannot receive more data. We should check the RXE bit of the I2C0FCN1 register to know if there is data in the FIFO and read the received data from the I2C0DIN register.

The auto-ACK feature makes flow control difficult, as mentioned above, when the RX FIFO is full, SCL is held low so the device can process the data. How can the masster change the read/write direction? There is another feature that can help with this situation. The FACS bit field of the I2C0ADM register. The default value is "1", which means FORCE_STRETCH. When this bit is 1, clock stretching always occurs after the ACK of the address byte until the firmware clears the I2C0INT bit. With this clock stretching feature, we can do flow control during read/write direction changes.

There is an I2C Slave bootloader example code based on AN945, please check it out and refer to the working principle of the I2C Slave machine state machine. The I2C Slave state machine can be seen in the two flow charts in the reference manual (Figure 17.7 and Figure 17.8), and can be condensed into this state decoding table (Table 17.1 - Table 17.8 in the reference manual).

https://www.silabs.com/documents/public/reference-manuals/efm8bb3-rm.pdf)

The working principle of I2C Bootloader is similar to SMBus Bootloader, see AN945 -

https://www.silabs.com/documents/public/application-notes/an945-efm8-factory-bootloader-user-guide.pdf. The boot_I2C.c file in the attachment shows how the I2CSlave peripheral is used - One may notice that only three states are defined in the code, while the table shown above describes many more. There are several reasons why some states are not included in the bootloader code -

1. The bootloader code is written in such a way that some of the above situations can never happen, and even if they do happen, they can be tied together by default. We are mainly concerned with the RD, WR, and RD+NACK states.

2. The bootloader's code is limited by size. We try to fit it into one Flash page, which in turn means we include only the code necessary for the bootloader to run, rather than accounting for cases that will never happen.

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