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I was stunned! There is actually an MCU with built-in logic analyzer function? ?

Latest update time:2024-11-01
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1. Let’s chat

I have several logic analyzers, such as DSlogic from Mengyuan, PXlogic from Octopus, and Selease from Jinshatan. These solutions are all FPGA, and their acquisition performance is beyond doubt. I once wanted to try DIY on MCU to satisfy my craving.


When I was reading the user manual of HPM6E00, I found a new peripheral in the GPIO chapter - LOBS, logic observation module. It was like a sudden sense of freshness after being tired of the same old GPIO, and it also started the journey of exploring this peripheral. From the perspective of peripheral functions, the main function is trace gpio, which can collect the specified number of gpio states before and after the trigger.



This article also uses this peripheral to simply build the basic collection and reporting function, and simply DIY a 32-channel pluseview-based logic analyzer, which corresponds to the 32 pins of PORT. The GPIO status of each channel is collected, stored and reported through the lobs peripheral.


Again, source code link:

https://github.com/RCSN/hpm_sdk_extra.git

The path is in demos/digital_logic_analyzer_hpm_for_pulseview.


2. Take a look

For the HPM6E00 of Xianji, when it was released, the ethercat peripheral seemed to overshadow other peripherals of this MCU, making people think that the highlight was ethercat. However, the highlight is not just ethercat. There are also other new peripherals and increased functions of existing peripherals, such as the Lobs logic observation module in this article.


The functions of this peripheral are quite rich, and the description of the internal chapter registers is also quite complete. The official description of the functions of this peripheral is generally summarized in one or two sentences. This article will briefly explain the function description. For more detailed content, please refer to the user manual and the lobs example of hpm_sdk.



3. Explore

1. What expected conditions will be sent to LOBS for collection?

Note: DI here represents the input signal level of GPIO, DO represents the output signal level of GPIO, and OE represents whether the attribute of GPIO is input or output.


According to the official configuration instructions, it can be triggered by two conditions. In simple terms, it can be triggered by the input pin of the timer, and the other is triggered by the internal counter count reload.


1. LOBS has a total of 5 trigger state arrays. After each group of triggers is completed, they can point to each other through the NETSTATE register. Each state can only specify one GPIO PORT.


2. When the NEXTSTATE of the state is 0, it means the trigger acquisition is complete. If you need to trigger it again next time, you need to reopen the acquisition.

The simple understanding is:

For the trigger signal, when the input detects a high level or a low level, the corresponding stata starts triggering the acquisition, and the level trigger depends on the set golden value.


Encapsulation processing is also done in the SDK. For example, if the triggered signal PF26 has a golden value of true, then it is a high-level trigger acquisition.


For counter triggering, it can be understood that the counter stops collecting when it counts to the comparison value, and the comparison value is the number of collections.


(II) How to store GPIO values

LOBs supports two modes, one is single group and the other is dual group. In simple terms, a state can either collect data from a single gpio port or two gpio ports. Both modes occupy 128 bits of memory, or 16 bytes.


A single group can collect the pins of the entire port. Each pin occupies 3 bits. The effective occupied 128 bits is 3*32=96 bits. The upper 32 bits are occupied by fixed bytes. The manual describes it as follows:


The gpio order corresponding to the valid bits is as follows:


Here we can simply encapsulate it with a structure, so that we can read the DI/DO/OE of each Pin through the bit field.


For dual groups, it should be noted that only 8 bits are effective, which is the minimum 8 bits for storage, but the required memory occupancy is also 128 bits. The convenience is that you can only collect the signals of the pins you are concerned about, such as DI or DO or OE, which are also displayed in the SDK.


The code in this article mainly refers to sample-lobs of hpm_sdk, and is split and explained according to the above functional description.


This sample mainly demonstrates the trace function of LOBs, which can monitor the GPIO status before and after the trace is triggered. From the readme, you can see:

Here we explain it with a single group:


1. The collection length of the group is 1024 data records, which is mainly reflected in the start and end addresses of the assignment. LOBs will automatically calculate the total collection length.


2. Set the trigger mode before the signal is triggered in state0, for example, use signal trigger, select the trigger signal, and point the trigger to state1. Note that the trigger signal can only be selected in the state setting group. For example, if the state is set to PA, the trigger signal can only be selected between PA00 and PA31.


3. Set the trigger mode after the signal is triggered in state1, such as using counter comparison trigger and comparison value setting. The comparison value is set to 1024-64=960 data. That is to say, 64 data will be collected before state0 is triggered. It does not point to the next state, and the current state is the last state.


4. Test

In order to visually check whether the LOBs data is collected accurately, the data can be collected and displayed through the PluseView host computer. The PluseView logic analyzer is not introduced here. The protocol uses the SUMP protocol and serial port communication can be used. Here, in order to facilitate the use of the USB CDC function, the reference example used is the CherryUSB CDC ACM example in the SDK.


You need to tell pluseview the current model, sampling rate, etc.


When receiving the meta command of sump, send the above data to the host computer


Open pluseview, select the following, the host computer will detect the corresponding device, click Ok.


A 32-channel device appears.


When the run command is received, lobs collection is turned on, and when the reset command is received, the collection is turned off.


When closing and opening Lobs, you need to unlock it. It is best to lock it after configuration. The corresponding api is as follows.


Open Lobs collection


Close lobs collection


Here only one state is used, the mode is single group 128bit, so the state is set to the last one, signal acquisition is not used, and only counter comparison is used. As follows:


Perform some conversion on the collected Buffer


Final report


The group used here is 5, and the corresponding ports are PF00~PF31

Introduce a PWM to the PF9 pin, start pluseview acquisition, and you can see that channel 9 has acquired PWM.


5. Conclusion

This article introduces a simple DIY logic analyzer function to stimulate discussion. We hope that we can explore and dig out more uses together.




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