PCIe 7.0, the latest sharing

Latest update time：2024-08-16

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Source: Content Compiled from anandtech , thank you.

As PCIe 5.0 deployments continue to heat up in the data center and consumer markets, PCI-SIG has not been sitting idle, but has begun to prepare the ecosystem for the update of the PCIe specification. At FMS 2024, some vendors were even talking about PCIe 7.0 with 128 GT/s capabilities, even though PCIe 6.0 has not even started shipping yet. We interviewed PCI-SIG to get the latest developments in its activities and discuss the current state of the PCIe ecosystem.

PCI-SIG has made the PCIe 7.0 specification (v 0.5) available to its members and expects the full specification to be officially released sometime in 2025. The goal is to achieve 128 GT/s data rates and up to 512 GBps bidirectional traffic using x16 links. Similar to PCIe 6.0, this specification will also utilize PAM4 signaling and maintain backward compatibility. Power efficiency and silicon area were also taken into consideration during the drafting process.

The move to PAM4 signaling introduces higher bit error rates compared to the previous NRZ scheme. This necessitated a different error correction scheme for PCIe 6.0 - rather than operating on variable-length packets, PCIe 6.0's Flow Control Element (FLIT) encoding operates on fixed-size packets to aid forward error correction. PCIe 7.0 retains these aspects.

The list of integrators for the PCIe 6.0 compliance program is also expected to be announced in 2025, although initial testing is already underway. This was reflected in the FMS 2024 demonstration involving Cadence's 3nm test chip (for its PCIe 6.0 IP products) and Teledyne Lecroy's PCIe 6.0 analyzer. These timelines are consistent with the specification completion dates and compliance program availability of previous generations of PCIe.

We also received an update on the Optical Working Group - while the group is optical technology agnostic, it also intends to develop technology-specific form factors including pluggable optical transceivers, on-board optics, co-packaged optics, and optical I/O. The logical and electrical layers of the PCIe 6.0 specification are being enhanced to accommodate the new optical PCIe standardization, a process that will also be completed in PCIe 7.0 to coincide with the release of that standard next year.

PCI-SIG 也有正在进行的布线计划。在消费者方面，我们看到 Thunderbolt 和外部 GPU 机箱的吸引力显著增加。然而，数据中心和企业系统也正在转向布线解决方案，因为很明显，将存储等组件与 CPU 和 GPU 分开更有利于热设计。此外，对于板载信号线来说，在较长的距离上保持信号完整性变得困难。计算系统内部的布线可以提供帮助。

OCuLink emerged as a good candidate and is widely used as an internal link in server systems. It even appears in some mini PCs from Chinese manufacturers in external incarnations for the consumer market, albeit with limited appeal. As speeds increase, a widely adopted standard for external PCIe peripherals (and even for connecting components within systems) will become imperative.

Reference Links

https://www.anandtech.com/show/21531/pcisig-demonstrates-pcie-60-interoperability-at-fms-2024

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