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When I first started using desktop computers, I took them apart and looked at the complex motherboards filled with various slots, chips, and other electronic devices. I always had a question: who can figure out all this mess? As I learned more about computer structures and PCB design of peripheral devices, I began to appreciate the contributions that PCB designers have made in building outstanding electronic devices.

Modern GPUs, USB, audio, and network cards all run on the back of the same computer peripheral architecture, PCI Express. If you're new to PCB design for PCIe devices, you'll find that information on the subject is fragmented, with some of it even closely guarded as company secrets. Fortunately, the basic specifications can be broken down into executable design rules. With the right PCB design software, you can easily lay out and route your next PCIe device.

Line wiring specifications

All three PCIe generations allow for longer trace lengths than most high-speed devices. Each generation has its own impedance and maximum trace length specifications for different data rates that should be followed closely to achieve and maintain the desired performance. The exact routing specifications depend on which PCIe generation you are using in your design.

Trace lengths in both Gen1 and Gen2 allow up to 21 inches for RX and TX signal traces, while Gen3 only allows trace lengths of up to 14 inches on these signal traces. To keep impedance within the specification, each TX trace pair can only contain a maximum of 2 vias, while the RX pair can only contain a maximum of 4 vias. For traces on the COM Express carrier board that are sent to the PCIe slot, both Gen1 and Gen2 support a maximum trace length of up to 9 inches.

The differential impedance of the signal lines depends on the bus used to connect the PCIe board. Standard PCBs with differential pair routing typically use 100 ohm differential impedance. The PCI-SIG bus for the first generation used the same standard, while the PCI-SIG bus for the second and third generations used 85 ohm differential impedance. The COMCDG 1.0 bus for PCIe Gen1 and Gen2 only required 92 ohm differential impedance, which is not compatible with PCIe Gen3. As an alternative, Gen3 used the COMCDG 2.0 bus to be compatible with PCIe Gen3 and specified a differential impedance of 85 ohms.

Different PCIe generations and bus standards have different tolerances for differential impedance values. Although the values are different for each bus standard and PCIe generation combination, you can find these specific values in the COMCDG 2.0 specification.

Keeping microstrip line impedance within tolerance is much easier when the PCB design software includes controlled impedance routing capabilities. Impedance tolerances can be specified directly in the design software, and the automatic routing or interactive routing tools will ensure that the traces are placed with the correct geometry and spacing.

Different PCIe generations and bus standards have different tolerances for differential impedance values. Although the values are different for each bus standard and PCIe generation combination, these specific values can be found in the COMCDG 2.0 specification.

Keeping microstrip line impedance within tolerance is much easier when the PCB design software includes controlled impedance routing capabilities. Impedance tolerances can be specified directly in the design software, and the automatic routing or interactive routing tools will ensure that the traces are placed with the correct geometry and spacing.

PCIe riser extenders plugged into a motherboard

Stacking and Grounding

A typical PCIe board uses a 4-layer stackup with two internal power planes and two signal planes. Different bias levels can be set for each power plane, depending on the device requirements. Some designers choose a 6-layer stackup with two signal planes running between the two power planes. Some guidelines also apply to 8-layer and 10-layer stackups for PCIe boards.

In some PCIe boards with 6-layer stackups, one of the power planes can be replaced with a ground plane. In both cases, signal traces routed on the inner layers will have better immunity to EMI. It is also possible to route traces at different data rates on different layers. On mixed-signal boards (such as in Wi-Fi or other wireless devices on PCIe cards), RF signal lines can be routed on inner layers and digital signal lines on outer layers. The ground/power plane will effectively block noise from reaching sensitive analog signal traces.

Whichever stackup you use, you need to make sure the overall thickness of the board matches the standard 1mm thickness for all PCIe cards. You also need to be mindful of standard high-speed design techniques, since PCIe Gen 1 runs at 2.5 GHz clock speeds, and signal speeds only increased with Gen 2 and Gen 3.

Traces routed on a PCB with blue solder mask

Pins, Pads, and Breakout Routing

It is especially important to route around obstacles and accommodate components and vias on the PCIe board. Routing to pins, pads, components, and BGA breakouts should be symmetrical. Differential pairs should be tightly coupled throughout their length, meaning any changes on one trace due to pads, vias, or components should be mirrored on adjacent traces. This ensures that crosstalk is suppressed across the differential pair. Note that this practice provides good crosstalk suppression in any high-speed system.

The same applies to shunt routing from a BGA or other component. For example, routing to a BGA will require a bend in one trace to reach one of the pads. If possible, the same bend should occur on the other trace. In addition, differential pairs should be routed together between adjacent pads on the BGA, rather than using pads between traces for routing.