Awesome LDO circuit
Latest update time：2021-11-14
Reads：
Source: Content from Semiconductor Industry Observer (ID: icbank) reprinted from the official account Yuezhi.com , author: Keith A. Bowman , thank you.
You’ve probably played hundreds of videos on your smartphone,
but have you ever wondered what happens when you press “play”? • A lot happens at once when you hit that little triangle button. Within microseconds, idle computing cores on your phone’s processor fire up. At the same time, their voltages and clock frequencies quickly ramp up to ensure that the video can be decompressed and displayed without delay. Meanwhile, other cores running tasks in the background slow down. Charge rushes through the millions of transistors in the active cores and slows to a trickle in the newly idle ones. • This pulsing, called dynamic voltage and frequency scaling (DVFS), happens constantly in the processors of the system-on-chip (SoC) that powers phones, laptops, and servers. It’s all about balancing computing performance with power consumption, which is particularly challenging in smartphones. The circuits that apply DVFS, which try to ensure that clock and voltage levels are stable and reliable when current surges, are also some of the hardest to design.
This is mainly because the clock generation and voltage regulation circuits are unlike anything on a smartphone SoC; they are analog circuits. Thanks to advances in semiconductor manufacturing, we have become increasingly accustomed to new processors with greatly increased computing power appearing every year. “Porting” a digital design from an old semiconductor process to a new one is no easy task, but it’s nothing compared to trying to port analog circuits to a new process. The analog components that implement DVFS, especially a type of circuit called a “low dropout regulator” (LDO), do not scale down like digital circuits do, and must be redesigned from scratch for essentially every new generation of products.
If we can make LDOs or other analog circuits with digital components, then the difficulty of transplantation will be greatly reduced, thus saving a lot of design costs and freeing engineers to solve other problems faced by cutting-edge chip design. In addition, the digital LDOs made in this way will be much smaller than analog LDOs and perform better in some aspects. Research teams in industry and academia have tested at least a dozen designs in the past few years, and although there are still some shortcomings, commercially useful digital LDOs may soon be realized.
The typical smartphone SoC is a marvel of integration.
It combines multiple central processing unit (CPU) cores, a graphics processing unit, a digital signal processor, a neural processing unit, an image signal processor, a modem, and other specialized logic blocks on a single piece of silicon. Of course, increasing the frequency of the clock driving these logic blocks will increase the speed at which they can complete their work. However, to operate at higher frequencies, higher voltages are also required. Otherwise, the transistors cannot be turned on or off before the next tick of the processor clock. Of course, higher frequencies and voltages come at the cost of power consumption. So, depending on the balance between energy efficiency and performance required to complete the assigned work (shooting a video, playing a music file, transmitting voice in a call, etc.), these cores and logic units dynamically change their clock frequency and supply voltage, usually between 0.95 and 0.45 volts.
Typically, an external power management integrated circuit generates multiple input voltage (
V
IN
) values for the mobile phone SoC. These voltages are delivered to various areas of the SoC chip along wide connecting lines called "rails", but the number of connections between the power management chip and the SoC is limited, so multiple cores on the SoC must share the same
V
IN
rail.
However, they don’t all have to be the same voltage, thanks to low-dropout regulators. LDOs, along with dedicated clock generators, allow each core on a shared rail to run at its own supply voltage and clock frequency. The core that requires the highest supply voltage determines the shared
VIN
value
. The power management chip
sets
VIN
to this value,
and
the core bypasses the LDO via a transistor called a “head switch.”
To minimize power consumption, other cores can operate at a lower supply voltage. Software determines what this voltage should be, and analog LDOs do a pretty good job of providing it. They are compact, cheap to manufacture, and relatively simple to integrate on a chip because they don't require large inductors or capacitors.
However, these LDOs can only operate within a certain voltage window. At its highest value, the target voltage must be lower than
the difference between
V
IN
and the voltage drop of the LDO itself (also called the "dropout voltage"). For example, if the core's most efficient supply voltage is 0.85 volts, but
V
IN
is 0.95 volts and the LDO's dropout voltage is 0.15 volts, the core cannot use the LDO to achieve 0.85 volts and must instead operate at 0.95 volts, wasting some power. Similarly, if
V
IN
is already set below a certain voltage limit, the analog components of the LDO will not work properly and the circuit cannot further reduce the supply voltage of the core.
If the desired voltage falls within the LDO's window, the software enables the circuit and activates a reference voltage equal to the target supply voltage.
So how does an LDO provide the right voltage?
In a basic analog LDO design, it's implemented with an op amp, feedback, and a dedicated power p-channel field-effect transistor (PFET). The latter is a transistor that reduces its current as voltage increases to its gate. The gate voltage of this power PFET comes from an analog signal from the op amp, which ranges between 0 volts and
V
IN
. The op amp continuously compares the circuit's output voltage (the core's supply voltage, or
V
DD
) to a target reference voltage. If the LDO's output voltage drops below the reference voltage, as it does when newly activated logic suddenly requires more current, the op amp reduces the power PFET's gate voltage, increasing current and
raising
V
DD
to the reference voltage value. Conversely, if the output voltage rises above the reference voltage, as it does when the core's logic is less active, the op amp raises the transistor's gate voltage to reduce current and
V
DD
.
A basic digital LDO, on the other hand, consists of a voltage comparator, control logic, and multiple power PFETs connected in parallel. (The LDO also has its own clock circuit, separate from that used by the processor core.) In a digital LDO, the gate voltage of the power PFET is a binary value rather than an analog value, so it is either 0 volts or
V
IN
.
With each tick of the clock, the comparator measures whether the output voltage is below or above the target voltage provided by the reference source. The comparator output guides the control logic to determine how many power PFETs to activate. If the output of the LDO is below the target value, the control logic activates more power PFETs. Their combined current supports the supply voltage of the core, and this value is fed back to the comparator to make it consistent with the target. If it is above the target value, the comparator sends a signal to the control logic to turn off some PFETs.
Of course,
neither analog nor digital LDOs are ideal. The main advantage of analog design is that it can respond quickly to transient drops and overshoots in the supply voltage, which is especially important when sharp changes are involved. These transients occur because the current demand of a core can rise or fall dramatically in a matter of nanoseconds. In addition to its fast response, the analog LDO also does a good job of rejecting
changes in
V
IN
from other cores on the rail
. Finally, it also tightly controls the output when the current demand does not change much, without constantly overshooting and undershooting the target in a way that introduces ripple in
V
DD
.
These characteristics make analog LDOs advantageous not only in supplying processor cores, but in nearly any circuit requiring a quiet, stable supply voltage. However, there are key challenges that limit the effectiveness of these designs. First, analog components are much more complex than digital logic, and implementing them at advanced technology nodes requires a long design time. Second, they do not function properly
at lower
V
IN
, limiting
the lowest value of
V
DD
they can deliver to the core
. Finally, the voltage dropout of analog LDOs is not as small as designers would like.
Combining these last points, analog LDOs offer a limited voltage window in which they can operate. This means that power savings achieved with LDOs, which could significantly improve smartphone battery life, cannot be achieved.
Digital LDOs address many of their weaknesses: Without complex analog components, designers can take advantage of a wealth of tools and other resources for digital design. Therefore, less work is required to reduce the size of the circuit to use a new process technology. Digital LDOs will also operate over a wider voltage range. On the low voltage side, digital components can operate at
V
IN
values that exceed the range of analog components. On the high voltage side, the voltage difference of digital LDOs will be smaller, effectively saving core power.
However, everything has its pros and cons, and digital LDOs have some serious disadvantages. Most of these are because the circuit only measures and changes its output intermittently, rather than continuously. This means that the circuit is relatively slow to respond to supply voltage drops and overshoots. It is
also more sensitive to changes in
V
IN
and tends to produce small fluctuations in the output voltage, both of which can degrade the performance of the core.
Currently, the main obstacle limiting the use of digital LDOs is their slow transient response. When the current drawn by the core changes abruptly in response to changes in its workload, the core experiences droops and overshoots. To limit the extent and duration of the voltage droop, the LDO’s response time to the droop event is critical. Traditional cores add a safety margin to the supply voltage to ensure that it operates properly during droops. More expected droops means that the margin must be larger, which reduces the energy efficiency benefits of the LDO. Therefore, speeding up the digital LDO’s response to droops and overshoots is a major focus of cutting-edge research in this field.
Several recent advances have helped speed up the circuit’s response to droop and overshoot.
One approach uses the digital LDO’s clock frequency as a control knob, trading stability and power efficiency for response time.
Lower frequencies improve the stability of the LDO because the output does not change as often. It also reduces the power consumption of the LDO because the transistors that make up the LDO switch less frequently. However, the trade-off is a slower response to transient current demands from the processor core. If you think about it, if the frequency is too low, a transient event can occur within a single clock cycle, so this happens.
A high LDO clock frequency actually improves transient response time because the comparator samples the output frequently enough to change the LDO output current before the transient event occurs. However, this constant sampling reduces output stability and consumes more power.
The point of this approach is to introduce a clock whose frequency can adapt to this situation, that is, an adaptive sampling frequency method that reduces dynamic stability. When the voltage drops or overshoots beyond a certain level, the clock frequency is increased to reduce transient effects more quickly. It then slows down to consume less power and keep the output voltage stable. This effect is achieved by adding an additional pair of comparators to detect overshoot and sag conditions and trigger the clock. When measuring a test chip using this technology,
the voltage drop of
V
DD
was reduced from 210 mV to 90 mV, a 57% reduction compared to a standard digital LDO design. The time required for the voltage to recover to a stable state was reduced from 5.8 microseconds to 1.1 microseconds, a reduction of 81%.
Another way to improve transient response time is to add a little analog to a digital LDO. This design integrates a separate analog auxiliary loop to respond instantly to load current transients. The analog auxiliary loop couples the LDO’s output voltage to the LDO’s shunt PFET through a capacitor, forming a feedback loop that engages only when the output voltage changes dramatically. Therefore, when the output voltage drops, it reduces the voltage at the activated PFET gate and momentarily increases the current flowing to the core to reduce the voltage drop. This analog auxiliary loop has been shown to reduce voltage drop from 300 mV to 106 mV (a 65% improvement) and overshoot from 80 mV to 70 mV (a 13% improvement).
Of course, both techniques have their own disadvantages. First, neither can truly match the response time of today's analog LDOs. In addition, the adaptive sampling frequency technique requires two additional comparators, and the generation and calibration of undershoot and overshoot reference voltages so that the circuit knows when to use a higher frequency. The analog auxiliary loop includes some analog components, which will reduce the design time benefits of a fully digital system.
The development of commercial SoC processors may help digital LDOs achieve greater success, even if they cannot completely match analog performance. Today, commercial SoC processors integrate fully digital adaptive circuits to mitigate performance issues when voltage drops occur. For example, these circuits temporarily extend the core's clock cycle to prevent timing errors. This mitigation technique can relax transient response time constraints, allowing the use of digital LDOs and improving processor efficiency. If so, we can look forward to more efficient smartphones and other computers, while making their design process easier and simpler.
*Disclaimer: This article is originally written by the author. The content of the article is the author's personal opinion. Semiconductor Industry Observer reprints it only to convey a different point of view. It does not mean that Semiconductor Industry Observer agrees or supports this point of view. If you have any objections, please contact Semiconductor Industry Observer.
Today is the 2858th content shared by "Semiconductor Industry Observer" for you, welcome to follow.
Recommended Reading
When will the chip shortage be alleviated? This is how the industry chain sees it
Japanese semiconductors, refuse to accept their fate
★ Why doesn’t the United States have lithography machines?
Semiconductor Industry Observation
" The first vertical media in semiconductor industry "
Real-time professional original depth
Scan the QR code , reply to the keywords below, and read more
Wafers｜ICs｜Equipment ｜Automotive Chips｜Storage｜TSMC｜AI｜Packaging
Reply
Submit your article
and read "How to become a member of "Semiconductor Industry Observer""
Reply Search and you can easily find other articles that interest you!
京公网安备 11010802033920号