The following is the basic principle block diagram of LDO. I don’t quite understand how to achieve constant voltage?

小太阳yy

The following is the basic principle block diagram of LDO. I don’t quite understand how to achieve constant voltage? [Copy link]

 

 

As shown in the figure above, the principle of the constant voltage output chip of LDO can be roughly analyzed as follows: the FB terminal of the error amplifier will remain equal to the VREF terminal. Then when the voltage of FB is equal to the voltage of VREF, what is the voltage output by the error amplifier?

Isn't it 0? Then how to control MOS? When the voltage of FB increases or decreases, the output of the error amplifier will also change, thereby driving MOS and adjusting the output voltage. Then how to ensure that the output voltage can control the voltage at both ends of MOS to be appropriate and ensure that the output voltage is what you want? I don't quite understand, closed-loop control? Please explain it to me.

maychang

"Please explain it to me"

The figure shows an op amp plus a P-channel MOS tube. The P-channel MOS tube is also a common-source amplifier, with output from the drain.

An amplifier, cascaded with another amplifier, is still an amplifier. Here, an op amp is cascaded with a P-channel MOS tube to form a new amplifier. If you look at this new amplifier carefully, you will understand how this circuit achieves constant voltage.

chunyang

Assuming that Vo rises for some reason, FB rises, the op amp output rises, the MOS tube gate voltage rises, and the MOS tube conduction degree decreases, which is equivalent to inserting a resistor with a higher resistance in series in the power supply loop, so Vo decreases. This is a negative feedback process until Vo stabilizes. Vice versa.

小太阳yy

chunyang published on 2022-5-19 13:09 Assuming that Vo rises for some reason, FB rises, the output of the op amp rises, the gate voltage of the MOS tube rises, and the conduction degree of the MOS tube decreases, which is equivalent to a series connection in the power supply circuit...

What is the output of the error amplifier in a stable state? I don't quite understand why the voltage output by the op amp to the MOS can just ensure that the voltage between the MOS DS can reach the output voltage we want.

小太阳yy

maychang posted on 2022-5-19 12:56 "Please explain it to me" The picture shows an op amp plus a P-channel MOS tube. The P-channel MOS tube is also a common source amplifier here, and the output is from the drain. ...

I don't quite understand. . Teacher, I don't understand how the voltage output by the error amplifier can control the MOS. How can it control the voltage across the MOS to the desired value? In other words, how does the error amplifier know how much voltage to output to control the MOS? Normally, isn't VFB = VREF? In this case, the amplifier output is 0, and if it is 0, how can the MOS work?

maychang

小太阳yy posted on 2022-5-19 14:22 I don't quite understand. . Teacher, I don't understand how the voltage control MOS output by the error amplifier can control the voltage across the MOS to the desired level...

"I don't understand how to control the voltage of the error amplifier output MOS. How can I control the voltage across the MOS to the desired value?"

The op amp controls MOS, which chunyang has already mentioned on the 3rd floor.

maychang

小太阳yy posted on 2022-5-19 14:22 I don't quite understand. . Teacher, I don't understand how the voltage control MOS output by the error amplifier can control the voltage across the MOS to the desired level...

"Isn't VFB = VREF in normal conditions? In that case, the amplifier output is 0, and if it is 0, how can the MOS work?"

Your understanding is wrong. VFB=VREF is the so-called "virtual short". At this time, the output of the op amp is not 0. It is unknown what it is. It may be greater than 0 or less than 0. VFB=VREF is the result of the infinite gain amplifier working under negative feedback, that is, the output of the MOS tube is divided by the two resistors R1R2.

maychang

小太阳yy posted on 2022-5-19 14:22 I don't quite understand. . Teacher, I don't understand how the voltage control MOS output by the error amplifier can control the voltage across the MOS to the desired level...

How does the error amplifier know how much voltage to output?

The operational amplifier is amplified by the MOS tube and then fed back to the op amp's common-mode input terminal through the R1R2 voltage divider .

maychang

小太阳yy posted on 2022-5-19 14:22 I don't quite understand. . Teacher, I don't understand how the voltage control MOS output by the error amplifier can control the voltage across the MOS to the desired level...

The first circuit uses a P-channel MOS tube. This circuit can also use an N-channel MOS tube or an NPN bipolar tube (the pros and cons are another issue). But when using an N-channel MOS tube or an NPN bipolar tube, the two input terminals of the op amp need to be swapped. Think about why they need to be swapped.

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小太阳yy

maychang posted on 2022-5-19 14:46 "If you don't understand the voltage control MOS output by the error amplifier, how can you control the voltage across the MOS to the desired value?" Op amp control...

Yes, teacher, I understand that the op amp controls the MOS, but I just don’t understand how the output of the op amp can just control the voltage across the MOS to get the final voltage value we want. . .

The output voltage is VO=VIN-V MOS_DS. Is there any problem with this formula?

Assume VIN=7v VO and we want 5V, then the voltage of VMOS DS is 7-5=2V

Then the voltage of VR2 should be 5*R2/(R1+R2). We make this voltage equal to the voltage of VREF.

If the voltage fluctuates and VIN becomes 8V, then if V0 is to be guaranteed to be 5V, the voltage of VMOS DS should be 3V.

The 2V and 3V voltages are controlled through calculation, but how do I know that the voltage output by the op amp added to the MOS will just ensure that the voltage on the MOS is 2V or 3V? Am I thinking something wrong?

maychang

Xiaoyangyy posted on 2022-5-19 15:29 Yes, teacher, I understand that the op amp controls the MOS, but I just don’t understand how the output of the op amp can just control the voltage across the MOS to get the best...

"If the voltage fluctuates and VIN becomes 8V, then if V0 is to be guaranteed to be 5V, then the voltage of VMOS DS should be 3V."

You are right. When the input voltage becomes 8V, the voltage between the MOS tube DS must be 3V to keep the output at 5V.

maychang

Xiaoyangyy posted on 2022-5-19 15:29 Yes, teacher, I understand that the op amp controls the MOS, but I just don’t understand how the output of the op amp can just control the voltage across the MOS to get the best...

"But how do I know that the voltage output by the op amp added to the MOS will just ensure that the voltage on the MOS is 2V or 3V?"

In fact, after the input voltage changes from 7V to 8V, the output voltage cannot maintain 5V, but is slightly higher than 5V, for example, 5.000001V. It is this 0.000001V voltage that makes the voltage between the MOS tube DS become 3V (actually a little less than 3V), as long as the DC gain of the op amp plus MOS is 1/0.000001, that is, 1000000. The DC gain of the op amp plus MOS can easily reach 1000000 times.

小太阳yy

maychang posted on 2022-5-19 15:39 "But how can I know that the voltage output by the op amp added to the MOS just guarantees that the voltage on the MOS is 2V or 3V?" In fact, the output voltage is...

I am even more confused when you put the op amp and MOS together. My understanding is that if a certain voltage is applied to the MOS G pole, the MOS tube will have a corresponding RDSON, that is, the output voltage of the op amp determines the RDSON of the MOS tube, but how can I be sure that the voltage output by the op amp can reach the RDSON value of the MOS I want? I still can't figure it out.

maychang

小太阳yy posted on 2022-5-19 16:31 I am even more confused when you put the op amp and MOS together. My understanding is that if a certain voltage is given to the MOS G pole, the MOS tube will have a corresponding RDSON, which means...

"But how can I be sure that the voltage output by the op amp can reach the RDSON value of the MOS I want? I still can't figure it out."

"Just reach", chunyang has made it clear on the 3rd floor. This is a negative feedback dynamic process, "until Vo stabilizes".

chunyang

小太阳yy posted on 2022-5-19 13:36 What is the output of the error amplifier in a stable state? I don't quite understand why the voltage output by the op amp to the MOS can just ensure the MOS DS...

The output of the op amp in steady state is unknown without parameter limits, and there is no need to know it, but this may make you even more confused. It is better to change the model, the essence is the same:

Suppose there is a power supply whose voltage may change, and the load is a resistor whose resistance value may also change. Now there is a potentiometer in series in the power supply-load loop. Your task is to adjust the potentiometer to keep the voltage across the load constant. Voltage observation is achieved by looking at a voltmeter with your eyes, and the resistance value of the potentiometer is controlled by your hand. Setting the voltage is your inner thoughts. This model is exactly the same as the original poster's picture. Here, the position of the potentiometer knob is equivalent to the output of the op amp in the original poster's picture, the potentiometer is the MOS tube in the original poster's picture, you are the op amp, and the voltmeter reading you see in your eyes is FB. Let me ask you, do you care about the position of the potentiometer knob? Do you need to make a scale? Obviously not, the only thing you have to do is to rotate the potentiometer, as long as the voltage can reach the value you want in your mind within the rotation range of the potentiometer. From this model, it should be easy to understand that the position of the potentiometer knob is related to the input voltage and the resistance value of the load resistor at the same time, and the same is true for the conduction degree of the MOS tube in the original poster's picture.

chunyang

As to why the output of the op amp can make the conduction degree of the MOS tube just maintain the stability of the output voltage, this is essentially a negative feedback process. Let's use the equivalent model mentioned above to illustrate: Assuming that the current load voltage deviates for some reason, you will definitely rotate the potentiometer to reduce the deviation. If you turn it too far, you will turn the potentiometer knob in reverse until you think the voltage is stable to the value you want. At this time, the voltage deviation you see with your eyes and the action of your hands constitute negative feedback. As long as your eyes and hands can keep up with the changes in the load voltage, the load voltage is stable.

小太阳yy

chunyang posted on 2022-5-19 16:58 The output of the op amp in steady state is unknown without parameter limitation, and there is no need to know it, but I am afraid that you are even more confused. It is better to change the model...

I understand what you said, but I am still a little confused about this error amplifier. I need to think about it carefully and discuss it with teachers. I feel that I may not have gotten started yet.

小太阳yy

maychang posted on 2022-5-19 16:36 "But how can I be sure that the voltage output by the op amp can just reach the RDSON value of the MOS I want? I still can't figure it out." "Just reach...

If MOS is removed, I think I can understand...

maychang

Xiaoyangyy posted on 2022-5-19 17:48 If MOS is removed, I think I can understand. . .

"If you remove MOS, I think I can understand it."

Remove the MOS, and the two input terminals of the op amp must be swapped, because the P-channel MOS has a common source, and the drain and gate are in opposite phases.