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[Shishuo Knowledge] Do you understand I2C Primer, PMBus and SMBus?

Latest update time：2022-01-19

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I ² C, or Inter-Integrated Circuit, is a commonly used serial communication protocol used to establish communication between devices, especially between two or more different circuits. I ² C Primer is the most commonly used I ² C. This article will introduce the basic characteristics and standards of I ² C Primer, and focus on how to correctly use this protocol in the communication implementation process. Starting from the basic principles of I ² C, we will introduce the availability of its variant subsets - System Management Bus (SMBus) and Power Management Bus (PMBus) - and the differences between the two. Each of these three protocols has specialized functions designed to meet different customer needs.

Why is it important?

I ² C helps designers establish simple, bidirectional, flexible communications between many nodes in a system. I ² C reduces complexity by using only two bidirectional lines to send and receive information. It also allows designers to configure communications between multiple master-node system ICs. I ² C also benefits developers who manage systems and power, allowing them to create high-quality products in the shortest possible time.

"Communication is useful to those who are devoted to it."

—John Powell

Communication protocols play an important role in organizing the communication between devices. It is designed in different ways based on the system requirements. Such protocols have clear, agreed-upon rules for successful communication.

If you've ever built a system using something like an LED display, a sensor, or even an accelerometer module, then you've most likely used I ² C. I ² C supports the ability for multiple nodes to connect to a single master, and multiple masters to connect to multiple nodes. This is useful if you want to maximize the use of a microcontroller to log data to a single memory card, or display text to a single LCD.

In addition to the most commonly used I ² C Primer, I ² C has two variants that focus on system and power applications, respectively, called the System Management Bus (SMBus) and the Power Management Bus (PMBus).

By definition, Inter-Integrated Circuit (I ² C) - also known as Inter IC - is a hardware communication protocol that allows synchronous communication over a multi-master, multi-node, serial communication bus. Synchronous communication means that two (or more) devices exchanging data share a common clock line. I ² C is widely used to connect low-speed peripheral ICs to processors and microcontrollers. The ^{I 2} C bus was designed by Philips to allow easy communication between devices on the same circuit board.

I2C Primer

interface

Minimize connections by using one serial data (SDA) line, one serial clock (SCL) line, and a common ground to carry all communications.

Figure 1. Integrated circuits communicate directly with each other.

Each I2C ^device has two lines:

SDA is the line used by masters and nodes to send and receive data.
SCL is the line that carries the clock signal. SCL is always generated by the ^I2C master. The specification has minimum period requirements for the low and high phases of the clock signal.

^{The I2C} bus uses only two bidirectional lines: SDA and SCL on each device for simple inter-IC communication.

Figure 2. I ² C pull-up resistor connection

The most important hardware consideration is to add pull-up resistors on SDA and SCL. ^I2C devices are connected to the bus through open-collector or open-drain pins, which pull the line low. When no data is being transmitted, the ^I2C bus is idle high; the line is passively pulled high. To transmit data, the line is toggled, i.e., pulled low and then released (high again). Data bits are transmitted on the falling edge of the clock.

The open-drain output requires a pull-up resistor (Rp in Figure 2) to correctly output a high level. The pull-up resistor is connected between the output pin and the output voltage required for the high level (V _DD in Figure 2 ).

For typical values of V _CC and V _DD (5 V), 4700 Ω is the most commonly used pull-up resistor value.

For reference, the capacitance of a shielded 2 AWG twisted pair cable ranges from 100 pF⁄m to 240 pF⁄m. Therefore, the maximum bus length for an I ² C link is about 1 meter at 100 kBaud or 10 meters at 10 kBaud. Unshielded cable typically has much less capacitance, but can only be used in an otherwise shielded enclosure.

Table 1 summarizes the key features of I ² C.

Table 1. I ² C Summary

Theoretically, the maximum number of nodes in the addressing mode is 2 ⁷ or 2 ¹⁰ , but 16 addresses are reserved for special purposes.

I2C is synchronous, so the output of the ^bits is synchronized with the sampling of the bits by a clock signal shared between the master and the nodes. The clock signal is always controlled by the master.

Reserved ^I2C node address

There are 16 reserved I ² C addresses. These addresses correspond to one of two patterns: 0000 XXX or 1111 XXX. Table 2 shows the I ² C addresses that are reserved for special purposes.

Table 2. I ² C Reserved Addresses

How I2C ^works

I2C data is transmitted in messages, which are broken down into data frames. The read and write protocol consists of an address frame (i.e., the binary address ^of the node) and another data frame, which contains the data being transmitted, start and stop conditions, a repeated start bit, a read/write bit, and an acknowledge/no acknowledge bit between each data frame.

Timing Specifications

The I2C timing table is also important because it allows engineers to design ICs that are compatible with the bus requirements. Each data rate has its own timing specifications that the master and nodes must adhere to in order to transfer data correctly ^.

Table 3 shows the symbols and parameters given on the timing specification table.

Table 3. Example of I ² C Timing Specifications

Figure 3. ^I2C message

I ² C transmission sub-protocol

A transfer on the bus is either a read or a write operation. The read and write protocols are built on a series of sub-protocols such as start and stop conditions, repeated start bits, address bytes, data transfer bits, and acknowledge/no acknowledge bits.

Starting conditions

As the name implies, the start condition always occurs at the beginning of a transmission and is initiated by the master device. This is done to wake up the idle node devices on the bus. The SDA line switches from high to low, and then the SCL line switches from high to low. See Figure 4.

Repeated start condition

The START condition can be repeated during a transfer without issuing a STOP condition. This is a special case called a repeated START and is used to change the direction of data transfer, repeat transfer attempts, synchronize multiple ICs, or even control serial memories. See Figure 5.

Address frame

The address frame consists of a 7-bit or 10-bit sequence, depending on availability (see data sheet). See Figure 6.

Unlike SPI, I2C ^does not have a node select line, so it needs another way to let a node know that data is being sent to it and not to another node. This is accomplished through addressing. The address frame is always the first frame after the start bit in a new message.

The master sends the address of the node it wants to communicate with to each node it is connected to. Each node then compares the address sent by the master with its own address. If the addresses match, it sends a low voltage ACK bit to the master. If the addresses do not match, the node does nothing and the SDA line remains high.

Read/Write bit

The last bit of the address frame tells the node whether the master wants to write data to it or receive data from it. If the master wants to send data to the node, the read/write bit is low. If the master requests data from the node, the bit is high. See Figure 7.

ACK⁄NACK bit

Each frame in the message is followed by an Acknowledge/Non-Acknowledge bit. If an address frame or data frame is successfully received, the receiving device returns an ACK bit to the sender.

Legend: In the following diagrams, white boxes represent nodes and blue boxes represent masters. See Figure 8.

Figure 4. Starting conditions

Figure 5. Repeated start condition

Figure 6. Address frame

Figure 7. Read/Write Bit

Figure 8. Acknowledge/Not Acknowledge Bit

Data Frame

Once the master detects the ACK bit from the node, it is ready to send the first data frame. Data frames are always 8 bits long and are sent MSB first. Each data frame is followed by an ACK⁄NACK bit to verify that the frame was successfully received. The master or node (depending on who is sending the data) must receive the ACK bit before sending the next data frame. See Figure 9.

Stop Condition

After sending all data frames, the master can send a stop condition to the node to stop the transmission. A stop condition is when the voltage on the SCL line changes from low to high, and then the voltage on the SDA line changes from low to high while the SCL line remains high.

After the SCL line switches from low to high, the SDA line switches from low to high. See Figure 10.

I ² C transfer steps: writing

See Figure 11 for an example of an I ² C transfer writing a single data .

step 1

The master toggles the SDA line from high to low and then toggles the SCL line from high to low to send a start condition to each connected node.

Step 2

The master sends the 7-bit or 10-bit address of the node with which it wants to communicate, along with the write operation bit, to each node.

For example, a 7-bit address of 0x2D plus the write bit (equivalent to 0) would result in 0x5A.

Step 3

Each node compares the address sent by the master with its own address. If the addresses match, the node pulls the SDA line low for one bit time to return an ACK bit. If the address from the master does not match the node's own address, the node leaves the SDA line high.

Pulling the SDA line low during the ninth pulse of SCL sends an ACK bit, while leaving it floating high sends a NACK.

Step 4

The master device sends or receives a data frame.

Step 5

After each data frame is transmitted, the receiving device returns an ACK bit to the sender to confirm successful receipt of the frame.

Step 6

To stop data transmission, the master should toggle SCL high and then toggle SDA high, thus sending a stop condition.

Figure 9. Data frame

Figure 10. Stop condition

Figure 11. Data sheet example of an I2C transfer writing to a single location

Figure 12. Data sheet example of an I2C transfer to read a single location

I ² C Data Transfer Steps: Read

step 1

The master toggles the SDA line from high to low and then toggles the SCL line from high to low to send a start condition to each connected node.

Step 2

The master sends the 7-bit or 10-bit address of the node with which it wants to communicate, along with the write operation bit, to each node.

For example, a 7-bit address of 0x2D plus the write bit (equivalent to 0) would result in 0x5A.

Step 3

Step 4

After the initial start, addressing, and acknowledgment, the master already knows the target node and the address to which it is pointing, so some devices have a repeated start condition to clean up the transaction.

NOTE: For reading purposes only!

Step 5

The master sends the 7-bit or 10-bit address of the node with which it wants to communicate, along with the read operation bit, to each node.

For example, a 7-bit address of 0x2D plus the read operation bit (equivalent to 1) would result in 0x5B.

Step 6

Step 7

After getting the ACK bit, the master receives the data frame from the node.

Step 8

After each data frame is transmitted, the master returns an ACK bit to the sender to confirm successful reception of the frame, or it returns a NACK if the read request has been completed.

Step 9

To stop data transmission, the master should toggle SCL high and then toggle SDA high, thus sending a stop condition.

Single Master and Multiple Nodes

I ² C uses addressing so a single master can control multiple nodes. Using 7-bit addresses provides 128 (2 ⁷ ) unique addresses. Using 10-bit addresses is less common but provides 1024 (2 ¹⁰ ) unique addresses. To connect multiple nodes to a single master, use 4.7 kΩ pull-up resistors between the nodes and connect the SDA and SCL lines to V _CC .

Multiple Masters and Multiple Nodes

Multiple masters can be connected to a single node or to multiple nodes. If there are multiple masters in the same system, problems can arise when two masters compete to send or receive data over the SDA line at the same time.

To solve this problem, each master device needs to detect whether the SDA line is low or high before transmitting a message.

If the SDA line is low, the bus is controlled by another master and the master should wait. If the SDA line is high, it can safely transmit a message. To connect multiple masters to multiple nodes, connect the SDA and SCL lines to V _CC using 4.7 kΩ pull-up resistors as shown in Figure 13 .

Figure 13. Multiple masters connecting multiple nodes

arbitration

Several I ² C multi-master devices can be connected to the same I ² C bus and operate simultaneously. They can determine if the bus is free by constantly monitoring SDA and SCL for start and stop conditions. If the bus is busy, the master device will delay pending I ² C transfers until a stop condition indicates that the bus is free again.

However, it may happen that two masters start transmitting at the same time. During the transmission, the masters constantly monitor SDA and SCL. If one of them detects that SDA is low, while it should be high, it will think that the other master is active and will stop the transmission immediately. This process is called arbitration. Both masters generate the start bit and continue their transmission.

If the master happens to select the same logic level, nothing happens.

Should the master attempt to apply a different logic level, the master pulling the signal low will be declared the winner; the loser will detect the logic mismatch and abandon the transmission.

Please take a moment to appreciate the simplicity and effectiveness of this arrangement:

The winner continues the transfer without interruption - no data corruption, no drive contention, no need to restart the transaction.
In theory, the loser could monitor the node addresses during the arbitration process, and if it happens to be the node being addressed, it could respond appropriately.
If competing masters all request data from the same node, the arbitration process does not unnecessarily interrupt either transaction—no mismatch is detected, the node outputs its data to the bus, and multiple masters can receive the data.

Clock stretch

Also called clock synchronization.

Note: The ^I2C specification does not define any time-out conditions for clock stretching—that is, any device can maintain SCL as long as necessary.

In the I ² C communication protocol, the clock speed and signals are always generated by the master device. The signals generated by the I ² C master provide synchronization between the master device and the node connection.

In some cases, a node or sub-node is not operating at full state and needs to be slowed down before receiving the clock generated by the master. This is achieved through a mechanism called "clock stretching".

During clock stretching, the node is allowed to pull the clock down in order to slow down the bus speed. On the master side, it must read back the clock signal after it goes high. Then, it must wait until the line reaches a high state.

bandwidth

While clock stretching is a common practice, it has an impact on bandwidth. When clock stretching is used, the overall bandwidth of a shared bus can be significantly reduced. Even with this technique, bus performance must still be reliable and fast. It is necessary to consider the estimated impact of using clock stretching, especially when multiple devices are sharing the I ² C bus.

Figure 14. Microcontroller data sheet

Clock stretching allows an ^I2C node device to force the master device into a wait state. A node device may perform clock stretching when it needs more time to manage data, such as storing received data or preparing to send another byte of data. This typically occurs after a node device receives and acknowledges receipt of a byte of data.

Which I ² C node devices require clock stretching?

Whether clock stretching is needed depends on the functionality of the node device. Here are two examples:

A processing device (such as a microprocessor or microcontroller) may require additional time to process interrupts, receive and manage data, and perform appropriate functions.
Simpler devices, such as EEPROMs, do not process data internally and therefore do not require clock stretching to perform any function.

I ² C Datasheet Example Example Overview

Different companies and manufacturers take different approaches to creating data sheets. Figure 13 shows a simple data sheet example with basic I ² C details, including registers and electrical specifications.

Figure 15. Microcontroller memory map

The most commonly used I ² C registers are shown in Table 4. The names and descriptions may vary from data sheet to data sheet, but the functionality and usage are the same.

Table 4. I ² C Register Descriptions

The creation of an I ² C may vary depending on the use case. Table 5 shows an example of a basic I ² C driver API requirement.

Table 5. I ² C driver development

SMBus

As we all know, SMBus can be used in applications where critical monitoring of parameters is required. Its most common applications are computer motherboards and embedded systems. It has additional monitoring specifications for temperature, supply voltage, fan monitoring and/or control integrated chips.

^{SMBus is a 2-wire bus similar to the I 2} C bus developed by Philips in the 1980s . The two main signals are clock (SMBCLK) and data (SMBDAT). The I ² C Primer and SMBus are compatible with each other, but there are significant differences, such as:

The SMBus logic level thresholds are fixed and not proportional to the device's supply voltage. Therefore, devices with different supply voltages can operate on the same Primer. For example, an SMBus may have multiple devices powered by 1.8 V, 3.3 V, and 5 V supplies.
They all run at the same speed up to 100 kHz, but the ^I2C Primer is available in 400 kHz and 2 MHz versions.
SMBus specifies a minimum clock speed and limits the amount the clock can be stretched in a transaction. Violating the timeout limit causes all SMBus devices to reset their I⁄O logic to allow the bus to restart. This design enhances the robustness of the bus.
The timeouts are also different. The ^I2C Primer has no timeout, while the SMBus does - for a minimum clock speed of 10 kHz, consider a timeout of 35 ms.
Packet Error Checking (PEC) was originally defined for the SMBus. A packet error code byte is added at the end of each transaction.
Some of the remaining differences involve the type of transmission, alarm line, pause line, shutdown or power-up.

Each time an SMBus device receives its own address, it must acknowledge (ACK) it, regardless of what it is doing. This is an explicit requirement to ensure that the master can accurately determine which devices are active on the bus.

All SMBus transactions are performed via one of the specified SMBus protocols.

The SMBus also has an optional signal, SMBALERT#, that a node device can use to quickly notify a master device or system host that it has information that the master device needs, such as reporting a fault condition.

Figure 16. SMBus topology

SMBus pull-up circuit

Figure 17. SMBus pull-up circuit

SMBus Address

The SMBus address has 7 binary bits, usually represented by the first 4 bits, the last 3 bits, and the last letter b, such as 0001 110b. These addresses occupy the upper 7 bits of an 8-bit field on the bus. However, the lowest bit of this field has another meaning and is not part of the range of SMBus addresses.

Figure 18. Node address

The 7-bit target address is sent from the master device to one or more devices on the bus (for example, via a broadcast address).

Note that the start and stop conditions are transitions, not bits, and the bit count is not shown above the symbol. When shown in a transaction diagram, a repeated start is also a transition, not a bit, and the bit count is not shown above the symbol.

Figure 19. SMBus message

SMBus timing measurements

Table 6. SMBus parameters

PMBus: Redefining Power Management

In addition to SMBus, there is also a variant, PMBus, which is an open standard power management protocol. This flexible and highly versatile standard allows communication between devices based on analog and digital technology and provides true interoperability, which will reduce the complexity of power system design and shorten time to market.

PMBus is used for digital management of power supplies with power control and management devices. It has commands and structures that support power management requirements. This means that I2C ^Primer and PMBus are compatible and interoperable in electrical requirements and command semantics.

One of the fundamental parameters of power management is overvoltage level monitoring, and PMBus provides commands to set and read this value. PMBus can be attached to the existing features of ^I2C Primer and SMBus, acting as a protocol layer on top of existing standards, especially SMBus.

The I2C specification describes only the physical layer, timing, and flow control of the 2-wire bus. ^{The I2C}^{specification} does not describe the format of the messages (like the SMBus protocol does), nor does it describe the content of the messages.

The PMBus specification is a complete power management protocol. It describes how bits and bytes are transferred from one device to another (i.e., transmitted). It also describes a command language that gives meaning to those bits and bytes.

Addressing

For redundant systems, once the power supply is installed in the system, there are up to three signals to set the address location of the power supply: Address 2, Address 1, and Address 0. For non-redundant systems, the power supply device address location should be B0h.

hardware

For I ² CV _DD based power supply and drive (for V _DD = 3.3 V), the devices in the power supply should be compatible with the SMBus 2.0 high power specification. The bus should run at 3.3 V.

power supply

The circuitry inside the power supply should be powered from the backup output. For redundant supplies, the device should be powered from the system side of the "logically ORed" device. The PMBus device should be on whenever AC power is present in the system power supply or in the paralleled redundant power supply.

Pull-up resistor

Only weak pull-up resistors can be used on the SCL or SDA lines internal to the power supply. The primary pull-up resistor is provided by the system and can be connected to either 3.3 V or 5 V. For system design, the primary pull-up resistor should be external to the power supply and draw power from the alternate power rail.

Data speed

PMBus devices in the power supply should run at the full 100 kbps SMBus speed and avoid clock stretching whenever possible because it slows down the bus.

Summarize

Table 8 outlines and summarizes the signal, timing, and electrical specifications for the I ² C Primer, SMBus (high power and low power), and PMBus.

How are the I ^{2
C Primer, SMBus, and PMBus related?}

SMBus was originally developed to assist battery management systems, using I ² C hardware, but a second level of software was added, which eventually allowed devices to be hot-swapped without rebooting the system. PMBus extends SMBus, defining a set of device commands specifically for managing power converters, exposing device properties such as measured voltage, current, temperature, etc. In general, I ² C Primer, SMBus, and PMBus devices can share the bus without major issues.

Advantages of I ² C, SMB, and PMB

Using only two lines
With ACK⁄NACK bit
Well-known protocol
Supports multiple masters and multiple nodes
Hardware is not as complex as UART
Widely used methods

shortcoming

Data transfer rate is slower than SPI
The data frame size is limited to 8 bits
The hardware required to implement is more complex than SPI

Figure 20. SMBus timing measurement

Table 7. PMBus Addressing

Example

Sensor reading
Sensor Write
EEPROM, temperature sensor, touch screen, proximity sensor
Transmit and control user-directed operations
Communicating with multiple microcontrollers
Consumer Electronics Devices
System Management
Power Management
debug

Table 8. Summary of I2C Primer, SMBus, and PMBus Specifications

Original article from Analog Devices

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