How to design a reliable digital interface for successive approximation ADCs?

The host processor can access or control the ADC through a variety of serial and parallel interfaces such as SPI, I ² C, and LVDS. This article discusses design techniques for creating reliable, complete digital interfaces, including digital power levels and sequencing, I/O states during startup, interface timing, signal quality, and errors due to digital activity.

Most SAR ADCs provide independent digital I/O power inputs (V _IO or V _DRIVE VDRIVE), which determines the operating voltage and logic compatibility of the interface. This pin should be at the same voltage as the host interface (MCU, DSP or FPGA) power supply. Digital inputs should generally be between DGND − 0.3 V and V _IO + 0.3 V to avoid violating absolute maximum ratings. A decoupling capacitor with a short trace length must be connected between the V _{IO pin and DGND.}

ADCs using multiple power supplies may have well-defined power-up sequences. Application Note AN-932 Power Supply Sequencing provides a good reference for the design of these ADC power supplies. In order to avoid forward biasing the ESD diode and preventing the digital core from being in an unknown state when powered on, the I/O power supply must be turned on before the interface circuit. Analog power is usually powered before I/O power, but this is not the case for all ADCs. Please refer to and follow the data sheet to ensure correct sequence.

To ensure proper initialization, some SAR ADCs require certain logic states or sequences to implement digital functions such as reset, standby, or shutdown. After all supplies are stable, the specified pulse or combination should be applied to ensure that the ADC starts up as expected. For example, a high pulse on RESET lasting at least 50 ns is required to configure the AD7606 for proper operation after power-up.

Digital pins must not be toggled until all power supplies are fully established. For SARADC, the conversion start pin CNVST may be sensitive to noise. In the example shown in Figure 1, the host cPLD pulls CNVST high while AVCC, DVCC, and V _DRIVE are still rising. This may put the AD7367 into an unknown state, so the host should hold CNVST low until power is fully established.

Figure 1. Pulling CNVST high during power-up may result in unknown conditions.

After the conversion is complete, the host can read the data through the serial or parallel interface. In order to read the data correctly, specific timing strategies must be followed, such as which mode the SPI bus needs to be in, etc. Digital interface timing specifications must not be violated, especially ADC and host setup and hold times. The maximum bitrate depends on the entire cycle, not just the minimum rated clock period. Figure 2 and the following equations show how to calculate setup and hold margin. The host sends the clock to the ADC and reads the data output by the ADC.

Figure 2. Establishing and holding timing slack.

t _CYCLE = t _JITTER + t _SETUP + t _{PROP_DATA} + t _{PROP_CLK} + t _DRV + t _MARGIN

t _CYCLE : clock cycle = 1/f _CLOCK

t _JITTER : clock jitter

t _SETUP : Host establishment time

t _HOLD : Host hold time

t _{PROP_DATA} : Data propagation delay of the transmission line from ADC to host

t _{PROP_CLK} : Data propagation delay of the transmission line from the host to the ADC

t _DRV : Data output valid time after clock rising/falling edge

t _MARGIN : If the margin time is greater than or equal to 0, it means that the setup time or hold time requirement is met, and if it is less than 0, it means that the setup time or hold time requirement is not met.

Host setup time margin

t _{MARGIN_SETUP} = t _CYCLE , min – t _JITTER – t _SETUP – t _{PROP_DATA} – t _{PROP_CLK} – t _DRV , _MAX

The settling time equation defines the minimum clock cycle time or maximum frequency in terms of the maximum system delay. To meet timing specifications, it must be greater than or equal to 0. Increase the period (lower the clock frequency) to solve the problem of excessive system latency. For buffers, level shifters, isolators, or other additional components on the bus, add additional delays to t _{PROP_CLK} and t _{PROP_DATA} .

Similarly, the host's hold time margin is

t _{MARGIN_HOLD} = t _{PROP_DATA} + t _{PROP_CLK} + t _DRV – t _JITTER – t _HOLD

The hold-time equation specifies the minimum system delay requirements to avoid logic errors due to violations of hold-time requirements. To meet timing specifications, it must be greater than or equal to 0.

Many SAR ADCs with SPI interfaces from Analog Devices provide the clock signal for the MSB from the falling edge of CS or CNV, and the remaining data bits follow the falling edge of SCLK, as shown in Figure 3. When reading MSB data, use t _EN instead of t _DRV in the equation .

Figure 3. AD7980 SPI timing in 3-wire CS mode.

Therefore, in addition to the maximum clock rate, the maximum operating rate of a digital interface also depends on setup time, hold time, data output valid time, propagation delay, and clock jitter.

In Figure 4, the DSP master accesses the AD7980 in 3-wire CS mode, where V _IO = 3.3 V. The DSP latches the SDO signal on the falling edge of SCLK. The DSP is rated for a minimum setup time of 5 ns and a minimum hold time of 2 ns. For a typical FR-4 PCB board, the propagation delay is approximately 180 ps/in. The propagation delay of the buffer is 5 ns. The total propagation delay of CNV, SCLK and SDO is

t _prop = 180 ps/in × (9 in + 3 in) + 5 ns = 7 ns.

t _JITTER = 1 ns. The host SCLK operates at 30 MHz, therefore, t _CYCLE = 33 ns.

t _{SETUP_MARGIN} = 33 ns − 1 ns – 5 ns – 7 ns – 11 ns – 7 ns = 2 ns

t _{HOLD_MARGIN} =11 ns + 7 ns + 7 ns – 1 ns – 2 ns = 22 ns

The setup and hold margins are both positive, so the SPI SCLK can operate at 30 MHz.

Figure 4. Digital interface between DSP and AD7980.

Digital signal integrity (including timing and signal quality) ensures: signals are received at rated voltage; do not interfere with each other; do not damage other devices; do not pollute the electromagnetic spectrum. Signal quality is defined by several terms, as shown in Figure 5. This section covers overshoot, ringing, reflections, and crosstalk.

Figure 5. Common signal quality specifications.

Reflections are the result of impedance mismatch. When a signal propagates along a trace, the instantaneous impedance at each interface is different. Some of the signal will be reflected back, and some of the signal will continue to travel along the line. Reflections can produce overshoot, undershoot, ringing, and non-monotonic clock edges at the receiver.

Overshoot and undershoot may damage the input protection circuitry or shorten the life of the IC. Figure 6 shows the absolute maximum ratings of the AD7606. The digital input voltage should be between –0.3 V and V _DRIVE + 0.3 V. Additionally, logic errors may result if ringing is above the maximum V _IL or less than the minimum V _{IH .}

Figure 6. AD7606 absolute maximum ratings.

To reduce reflections:

• Keep the length of traces as short as possible

• Control the characteristic impedance of traces

• Eliminate branches

• Use proper termination scheme

• Use solid metal with small loop area as the return current reference plane

• Use lower drive current and slew rate

For the calculation of trace characteristic impedance, there are currently many software tools or websites, such as Polar Instruments Si9000 PCB transmission line field solver. With these tools, characteristic impedance calculation is as simple as selecting a transmission line model and setting the appropriate parameters, such as dielectric type and thickness as well as trace width, thickness and isolation.

IBIS is an emerging standard used to describe the analog behavior of IC digital I/O. ADI provides IBIS models for SAR ADCs. Pre-layout simulation detects clock distribution, chip package type, board stackup, network topology and termination strategy. Serial interface timing constraints can also be detected to provide guidance for positioning and placement. Post-simulation verifies that the design complies with all guidelines and constraints while detecting reflections, ringing, crosstalk, and other violations.

In Figure 7, one driver is connected to SCLK1 through a 12-inch microstrip line, and the other driver is connected to SCLK2 through a 43 Ω resistor in series with the microstrip.

Figure 7. Driving AD7606 SCLK.

In Figure 8, the large overshoot on SCLK1 violates the absolute maximum rating of –0.3 V to +3.6 V. The series resistor reduces the slew rate on SCLK2 so that the signal is within specifications.

Figure 8. AD7606 IBIS overshoot model simulation.

Crosstalk is the coupling of energy between parallel transmission lines through mutual capacitance (electric field) or mutual inductance (magnetic field). The amount of crosstalk depends on the signal's rise time, the length of the parallel lines, and the spacing between them.

Some common methods of controlling crosstalk are:

• Increase line spacing

• Reduce parallel routing

• Keep traces close to the reference metal plane

• Use proper termination scheme

• Reduce signal slew rate

Digital activity can cause SAR ADC performance degradation, causing SNR to be reduced due to digital ground or power supply noise, sampling clock jitter, and digital signal interference.

Aperture or sampling clock jitter sets SNR limits, especially for high frequency input signals. System jitter comes from two sources: aperture jitter from the on-chip sample-and-hold circuit (internal jitter), and jitter on the sampling clock (external jitter). Aperture jitter is the change in sampling time between conversions as a function of the ADC. Sampling clock jitter is usually the dominant source of error, but both sources can cause variations in the analog input sampling time, as shown in Figure 9. Their effects are difficult to distinguish.

The total jitter creates an error voltage, and the limiting factor for the ADC's total SNR is

where f is the analog input frequency and t _J is the total clock jitter.

For example, when the analog input is 10 kHz and the total jitter is 1 ns, the SNR limit is 84 dB.

Figure 9. Error voltage due to sampling clock jitter.

Power supply noise caused by digital output switching should be isolated from sensitive analog supplies. Decouple analog and digital supplies separately, paying close attention to ground return paths.

High-precision SAR ADCs can be sensitive to activity on the digital interface, even when the power supply is properly decoupled and isolated. Burst clocks tend to be better than continuous clocks. Datasheets usually list quiet times during which the interface should be inactive. At higher throughput rates, it may be difficult to reduce digital activity during these times, typically sampling times and critical bit decision points.

Pay close attention to digital activity to ensure the SAR ADC conversions are valid. Errors caused by digital activity can put the SAR ADC into unknown states, causing malfunctions or degrading performance. Hopefully this article will help designers troubleshoot the root cause while also providing solutions.

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