【Shishuo Design】How to increase isolation for ADC without compromising its performance?

For isolated high-performance ADCs, attention should be paid to isolating the clock on the one hand, and isolating the power supply on the other. SAR ADCs have traditionally been used in lower sampling rate and lower resolution applications. Today there are fast, high-accuracy, 20-bit SAR ADCs with 1 MSPS sampling rates, such as the LTC2378-20, and oversampled SAR ADCs with 32-bit resolution, such as the LTC2500-32. When using ADCs for high-performance designs, the entire signal chain needs to be very low noise. When the signal chain requires additional isolation, performance suffers.

Regarding isolation, there are three aspects to consider:

• Make sure the hot end has an isolated power source

• Ensure the data path gets isolated isolated data

• Clock isolation of the ADC (sampling clock or conversion signal) in case the hot end does not generate the clock

Flyback converters are widely used for isolated power supplies. Figure 1 shows the simple and feasible features of a flyback converter. The advantage of this topology is that it requires few external components. Flyback converters have only one integrated switch. This switch can be a major source of noise affecting signal chain performance. For high-performance analog designs, flyback converters introduce many breakpoints, causing electromagnetic emissions (called EMI) that can limit the performance of the circuit.

Figure 1. Typical flyback converter topology.

Figure 2 shows the current flow in transformers L1 and L2. In the primary (L1) and secondary (L2) windings, the current jumps from a high value to zero in a short period of time. The current spike can be seen in the I(L1)/I(L2) trace in Figure 3. Current and energy accumulate in the primary inductor, and when the switch opens, they are transferred to the secondary inductor, creating a transient. Transients caused by switching noise effects need to be reduced, so buffers and filters must be inserted into the design. In addition to the additional filter, another disadvantage of the flyback topology is the low utilization of magnetic materials, while the required inductance is higher and therefore the transformer is larger. In addition, the thermal loop of a flyback converter is large and difficult to manage.

Another challenge with flyback converters involves switching frequency changes. Figure 3 shows the frequency changes caused by load changes. As shown in Figure 3a, t1 < t2. This means that f _SWITCH changes as the load current decreases from higher load current I1 to lower load current I2. Changes in frequency can create internal noise at unpredictable times. Additionally, the frequency will also vary from device to device, making it more difficult to filter as each PCB will need to adjust the filtering. For a 20-bit SAR ADC with a 5 V input range, 1 LSB is equivalent to approximately 5 μV. The error introduced by EMI noise should be less than 5μV, which means that a flyback topology should not be selected when isolating power supplies for precision systems.

There are other isolated power architectures with lower electromagnetic radiation disturbance. In terms of radiation, push-pull converters are more suitable than flyback converters. Push-pull regulators like the LT3999 offer the possibility to synchronize with the ADC clock, helping to achieve high performance. Figure 4 shows the LT3999 in an isolated power supply circuit synchronized with the ADC sampling clock. Remember, the primary-to-secondary capacitance provides a return path for switching noise that avoids the effects of common-mode noise. This capacitance can be implemented in the PCB design using overlapping top and second layer planes, as well as using actual capacitance.

Figure 2. The LT8301 switches current in a transformer winding.

Figure 3. (a) LT8301 frequency variation,

(b) Close-up of the frequency change from 2.13 ms to 2.23 ms.

Figure 4. LT3999 with ultra-low noise post regulator.

Figure 5. LT3999 current waveform.

Figure 6. LT3999 and its switching relationship with the synchronization pin.

Figure 5 shows the current waveforms at the transformer (primary and secondary side currents), which makes better use of the transformer and provides better EMI behavior.

Figure 6 shows synchronization with an external clock signal. The end of the acquisition phase is aligned with the positive edge of the sync pin. Therefore, there will be a longer quiet time of approximately 4μs. This allows the converter to sample the input signal within that time range and minimize the effects of transients on the isolated power supply. The LTC2378-20 has an acquisition time of 312 ns, which is ideal for the <1μs quiet window.

Data isolation can be achieved using digital isolators, such as the ADuMx series of digital isolators. These digital isolators can be used for many standard interfaces such as SPI, I2C, CAN, etc. For example, the ADuM140 can be used for SPI isolation. To achieve data isolation, simply connect the SPI signals SPI Clock, SDO, SCK and Busy to the data isolator. In data isolation, power is transferred from the primary side to the secondary side through an inductive isolation barrier. A current return path needs to be added, which is done by the capacitor. This capacitor can be implemented in the PCB using overlapping planes.

Clock isolation is another important task. If a 20-bit high-performance ADC with a 1 MHz sampling rate, such as the LTC2378-20, is used, a signal-to-noise ratio (SNR) of 104 dB can be achieved. To achieve high performance, a jitter-free clock is required. Why shouldn't standard isolators like the ADuM14x series be used? Standard isolators increase clock jitter, limiting the performance of the ADC.

Figure 7 shows the theoretical limits of SNR at different frequencies and types of clock jitter. A high-performance ADC like the LTC2378 has an aperture clock jitter of 4 ps, with a theoretical limit of 106 dB at a 200 kHz input.

Figure 7. Clock jitter versus ADC performance.

Figure 11 shows a more detailed block diagram of using a PLL to purify the clock. You can use the ADF4360-9 as a clock purifier and add a divider by 2 on the output. The AD7760 is rated to support 1.1 MHz.

Figure 8. Clock isolation using standard isolators.

The standard clock isolator concept shown in Figure 8 includes:

• A good standard digital isolator like the ADuM250N has a jitter of 70 ps rms. For the 100 dB SNR target, the signal sampling rate is limited to 20 kHz due to clock jitter.

• Optimized clock isolators like the LTM2893 provide low jitter of 30 ps rms. For the 100 dB SNR target, the signal is now sampled at 50 kHz, providing more bandwidth at full SNR performance.

Figure 9. Clock isolation using an LVDS clock isolator.

• Figure 9: For higher input frequencies, an LVDS isolator should be used. The ADN4654 provides 2.6 ps jitter, which is close to the ADC's best performance. At a 100 kHz input, the SNR limit due to clock jitter will be 110 dB.

Figure 10. Clock isolation using additional PLL to clean up clock jitter.

• Figure 10: Cleaning the clock using a PLL. The ADF4360-9 can help reduce clock jitter.

Figure 11. The ADF4360-9 is used as a clock purifier.

Therefore, 1 MSPS SAR ADCs such as the LTC2378 cannot be directly supported. In this case, a low-jitter flip-flop can help. It divides the clock by 2.

Figure 12. Flip-flop used to slow clock for LTC2378.

Figure 13. Clock generation on the isolated (thermal) side.

• Figure 13: Locally generated clocks are another option for obtaining clocks with the required jitter performance. Local clock generation makes the clock architecture more complex because it introduces asynchronous clock domains into the system. For example, if two separate isolated ADCs are used, the absolute frequency of the clocks will be different and sample rate conversion must be added to rematch the clocks. See Engineer Dialogue Note EE-268 for some details on sample rate conversion.

Similar issues with clocking apply to high-performance Sigma-Delta ADCs such as the AD7760. Here, the important clock signal is a jitter-free oversampled clock, such as 40 MHz. No additional divider is required in this case.

Isolated high-performance ADCs require careful isolation design and isolation technology selection to achieve high-performance SNR above 100 dB. Special attention should be paid to isolating clocks because the effects of clock jitter can disrupt performance. Secondly, attention should be paid to isolating the power supply. Simple isolation topologies such as flyback can introduce high EMI transients.

For better performance, push-pull converters should be used. There is also a need to pay attention to data isolation (although less important), and the standard devices available provide good performance with less impact on overall system performance. Introducing these three isolation topics can help designers come up with high-performance isolation system solutions.

Original text reproduced from Analog Devices

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