A phase compensation algorithm is used to compensate for the additional phase delay introduced by the multiplexed ADC, thereby producing an effect equivalent to a synchronously sampled ADC.
This design introduces the concepts of phase and phase compensation, compares the additional phase delay introduced between the input channels of an asynchronous sampling ADC and a synchronous sampling ADC, and provides an optimal algorithm to compensate for the phase introduced in an asynchronous sampling ADC Delay.
Measurements show how the phase compensation algorithm used in this design compensates for the additional phase delay introduced by multiplexed ADCs, resulting in a performance solution comparable to the simultaneous sampling ADC solution.
Blockdiagram
All reference designs on this site are sourced from major semiconductor manufacturers or collected online for learning and research. The copyright belongs to the semiconductor manufacturer or the original author. If you believe that the reference design of this site infringes upon your relevant rights and interests, please send us a rights notice. As a neutral platform service provider, we will take measures to delete the relevant content in accordance with relevant laws after receiving the relevant notice from the rights holder. Please send relevant notifications to email: bbs_service@eeworld.com.cn.
It is your responsibility to test the circuit yourself and determine its suitability for you. EEWorld will not be liable for direct, indirect, special, incidental, consequential or punitive damages arising from any cause or anything connected to any reference design used.
Supported by EEWorld Datasheet
EEWorld
subscription
account
EEWorld
service
account
Automotive
development
circle
About Us Customer Service Contact Information Datasheet Sitemap LatestNews
Room 1530, 15th Floor, Building B,
No.18 Zhongguancun Street,
Haidian District,
Beijing, Postal Code: 100190
China
Telephone: 008610 8235 0740
京公网安备 11010802033920号
XC9110F171MR
