How far can IC integration take phased array technology?

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Over the past few years, we have seen widespread use of parabolic dish antennas for transmitting and receiving signals in applications where directivity is important. Many of these systems perform very well and have remained relatively low cost after years of optimization. But these mechanically steered dishes have some drawbacks. They are bulky, slow to operate, have poor long-term reliability, and can only provide one desired radiation pattern or data stream.

Phased array antennas use an electrical signal steering mechanism and have many advantages, such as low height, small size, better long-term reliability, fast steering, and multiple beams. A key aspect of phased array antenna design is the spacing of antenna elements. Most arrays require element spacing of about half a wavelength, so more complex designs are required at higher frequencies, which drives ICs to achieve higher levels of integration and more advanced packaging solutions at higher frequencies.

There is a lot of interest in applying phased array antenna technology to a variety of applications. However, engineers have been limited by the ICs currently available to make phased array antennas a reality. Recently developed IC chipsets have successfully solved this problem. Semiconductor technology is moving towards advanced silicon ICs, which allows us to combine digital control, memory, and RF transistors into the same IC. In addition, gallium nitride (GaN) significantly improves the power density of power amplifiers and can help significantly reduce the footprint.

ICs have played a major role in the industry's transition to smaller arrays that are smaller and lighter. Traditional circuit board construction has essentially used a small PCB board with the electronics fed vertically into the back of the antenna PCB. Over the past 20 years, this approach has been continuously improved to continue to reduce the size of the board, thereby reducing the depth of the antenna. The next generation of designs moved from this board structure to a flat-panel approach, which greatly reduced the depth of the antenna, making it easier to fit them into portable or airborne applications. To achieve smaller sizes, each IC needs to be integrated enough to fit them into the back of the antenna.

In a planar array design, the space available for the IC behind the antenna is limited by the spacing between the antenna elements. For example, at scan angles up to 60°, the maximum antenna element spacing needs to be 0.54 λ to prevent grating lobes. Figure 1 shows the maximum element spacing in inches versus frequency. As frequency increases, the spacing between elements becomes very small, squeezing the space needed for components behind the antenna.

In Figure 2, the left image shows the gold patch antenna element on the top of the PCB, and the right image shows the antenna analog front end on the bottom of the PCB. It is also very typical in these designs to have frequency conversion stages and distribution networks on other layers. It is clear that using more integrated ICs can greatly reduce the difficulty of implementing antenna designs in the required space. After we pack more electronic components into a smaller size, which allows the antenna size to decrease, we need to adopt new semiconductor and packaging technologies to make the solution feasible.

The microwave and millimeter wave (mmW) IC components that serve as the building blocks of phased array antennas are shown in Figure 3. In the beamforming section, attenuators adjust the power level of each antenna element to reduce grating lobes in the antenna pattern. Phase shifters adjust the phase of each antenna element to steer the antenna main beam, and switches are used to switch between the transmitter and receiver paths. In the front-end IC section, a power amplifier is used to transmit the signal, a low noise amplifier is used to receive the signal, and finally, another switch is used to switch between the transmitter and receiver. In the past configurations, each IC was provided as a separate packaged device. More advanced solutions use integrated single-chip single-channel gallium arsenide (GaAs) ICs to perform this function. For most arrays, there is a passive RF combiner network, receiver/exciter, and signal processor preceding the beamformer, which is not shown in the figure.

The popularity of phased array antenna technology in recent years is inseparable from the development of semiconductor technology. Advanced nodes in SiGe BiCMOS, silicon on insulator (SOI), and bulk CMOS merge digital and RF circuits together. These ICs can perform digital tasks in the array, as well as control the RF signal path to achieve the required phase and amplitude adjustments. Today, we can realize multi-channel beamforming ICs that can adjust gain and phase in a 4-channel configuration, supporting up to 32 channels, which can be used for millimeter wave designs. In some low-power examples, silicon-based ICs have the potential to provide a single-chip solution for all of the above functions. In high-power applications, gallium nitride-based power amplifiers significantly increase power density and can be installed in the unit components of phased array antennas. These amplifiers have traditionally used traveling wave tube (TWT)-based technology or relatively low-power GaAs-based ICs.

In airborne applications, we see a growing trend toward flat-panel architectures because of the power-added efficiency (PAE) advantages of GaN technology. GaN also enables large ground-based radars to move from dish antennas driven by TWTs to phased-array-based antenna technology driven by solid-state GaN ICs. We can now use single-chip GaN ICs that can deliver over 100 W of power with PAE over 50%. Combining this efficiency level with the low duty cycle of radar applications allows for surface-mount solutions to dissipate the heat generated in the base of the enclosure. These surface-mount power amplifiers significantly reduce the size, weight, and cost of antenna arrays. Beyond the pure power capability of GaN, an additional benefit is the reduced size compared to existing GaAs IC solutions. For example, a 6 W to 8 W GaN-based power amplifier at X-band can reduce the footprint by 50% or more compared to a GaAs-based amplifier. This footprint reduction is significant when fitting these electronics into the unit building blocks of a phased-array antenna.

Developments in packaging technology have also significantly reduced the cost of planar antenna architectures. High-reliability designs may use a gold-plated hermetic housing with the chip and cables interconnected inside. These housings are more rugged in extreme environments, but are large and expensive. Multi-chip modules (MCMs) integrate multiple MMIC devices and passive components into a relatively low-cost surface-mount package. MCMs still allow for a mix of semiconductor technologies to maximize the performance of each device while significantly saving space. For example, a front-end IC may contain a PA, LNA, and T/R switch. Thermal vias or solid copper scrap in the package base are used to dissipate heat. To save costs, many commercial, defense, and aerospace applications have begun to use lower-cost surface-mount packaging options.

Integrated analog beamforming ICs, generally referred to as core chips, are designed to support a wide range of applications including radar, satellite communications, and 5G communications. The main function of these chips is to accurately set the relative gain and phase of each channel to increase the signal in the desired direction of the antenna's main beam. The beamforming IC is developed specifically for analog phased array applications or hybrid array architectures that combine some digital beamforming techniques with analog beamforming techniques.

The ADAR1000 X-/Ku-band beamforming IC is a 4-channel device covering the frequency band from 8 GHz to 16 GHz, using time division duplex (TDD) mode, with the transmitter and receiver integrated into one IC. In receive mode, the input signal passes through four receive channels and is combined at the common RF_IO pin. In transmit mode, the RF_IO input signal is decomposed and passed through four transmit channels. The functional block diagram is shown in Figure 4.

A simple 4-wire serial port interface (SPI) controls all on-chip registers. Two address pins provide SPI control of up to four devices on the same serial cable. Dedicated transmit and receive pins synchronize all core chips in the same array, and a single pin controls fast switching between transmit and receive modes. This 4-channel IC is packaged in a 7 mm × 7 mm QFN surface mount package for easy integration into flat panel arrays. The high level of integration, combined with a small package, addresses some of the size, weight, and power challenges of phased array architectures with a high number of channels. The device consumes only 240 mW/channel in transmit mode and 160 mW/channel in receive mode.

The transmit and receive channels are directly available and can be used with the front-end IC in an external design. Figure 5 shows the gain and phase diagram of the device. With full 360° phase coverage, phase steps of less than 2.8° and gain adjustments better than 30 dB can be achieved. The ADAR1000 integrates on-chip memory to store up to 121 beam states, one of which contains all phase and gain settings for the entire IC. The transmitter provides approximately 19 dB of gain and 15 dBm of saturated power, with a receive gain of approximately 14 dB. Another key indicator is the phase variation within the gain setting, which is approximately 3° over a 20 dB range. Similarly, the gain variation of the phase is approximately 0.25 dB over the entire 360° phase coverage, alleviating calibration challenges.

The ADTR1107 front-end IC complements the ADAR1000 beamforming chip. The ADTR1107 is a compact 6 GHz to 18 GHz front-end IC that includes an integrated power amplifier, a low noise amplifier (LNA), and a reflective single-pole double-throw (SPDT) switch. The functional block diagram is shown in Figure 6.

This front-end IC provides 25 dBm saturated output power (PSAT) and 22 dB small signal gain in the transmit state, and 18 dB small signal gain and 2.5 dB noise figure in the receive state (including T/R switch). The device is equipped with a bidirectional coupler for power detection. The input/output (I/O) is internally matched to 50 Ω. The ADTR1107 is packaged in a 5 mm × 5 mm, 24-lead land grid array (LGA) package. The transmit and receive gain and return loss of the ADTR1107 are shown in Figure 7.

The ADTR1107 is designed to be easily integrated with the ADAR1000. The interface schematic is shown in Figure 8. Four ADTR1107 ICs are driven by one ADAR1000 core chip. For simplicity, the diagram only shows the connection of one of the ADTR1107 ICs.

The ADAR1000 provides all the gate bias and control signals needed to interface seamlessly with the front-end IC. Although the ADTR1107 LNA gate voltage is self-biased, we can also control the voltage from the ADAR1000. The gate voltage of the ADTR1107 power amplifier is also provided by the ADAR1000. Since one ADAR1000 drives four ADTR1107s, four independent negative gate voltages are required to bias the power amplifier voltage. Each voltage is set by an 8-bit digital-to-analog converter (DAC). This voltage can be set by the ADAR1000 TR input or by writing to the serial peripheral interface. Setting the ADAR1000 TR pin toggles the polarity of the ADAR1000 between receive and transmit modes. The TR_SW_POS pin can drive the gates of up to four switches and can be used to control the ADTR1107 SPDT switch.

The ADTR1107 CPLR_OUT coupler output can be connected back to one of the four ADAR1000 RF detector inputs (DET1 to DET4 in Figure 4) to measure the transmit output power. These diode-based RF detectors have an input range of −20 dBm to +10 dBm. The coupling factor of the ADTR1107 directional coupler ranges from 28 dB at 6 GHz to 18 dB at 18 GHz.

The ADTR1107 can be pulsed by the gate voltage driven by the ADAR1000 while keeping the drain constant. This approach is more optimized than pulsing the drain because it uses a high power MOSFET switch and gate driver device and gate switch, which uses low current. It should also be noted that in transmit mode, the ADAR1000 provides enough power to saturate the ADTR1107, and the ADTR1107 can withstand the total reflected power when the antenna is shorted.

The combined performance of the ADTR1107 and ADAR1000 in transmit and receive modes over the 8 GHz to 16 GHz frequency range is shown in Figure 9. In transmit mode, they provide approximately 40 dB gain and 26 dBm saturated power, and in receive mode, they provide approximately 2.9 dB noise figure and 25 dB gain.

Figure 10 shows four ADAR1000 chips driving 16 ADTR1107 chips. A simple four-wire SPI controls all on-chip registers. Two address pins allow SPI control of up to four ADAR1000 chips on the same serial cable. Dedicated transmit and receive load pins also synchronize all core chips in the same array, and a single pin controls fast switching between transmit and receive modes.

Highly integrated RF transceiver chips can improve integration at the antenna level. ADRV9009 is a good example of such a chip. It provides dual transmitters and receivers, integrated frequency synthesizers, and digital signal processing functions. The device uses an advanced direct conversion receiver with high dynamic range, wide bandwidth, error calibration, and digital filtering. It also integrates a variety of auxiliary functions, such as analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), as well as general-purpose inputs/outputs for power amplifiers and RF front-end control. The high-performance phase-locked loop provides fractional-N RF frequency synthesis for both transmitter and receiver signal paths. It provides extremely low power consumption and a comprehensive shutdown mode to further save power when not in use. ADRV9009 adopts a 12 mm × 12 mm, 196-pin chip-scale ball grid array package.

Analog Devices provides the entire signal chain from antenna to position for phased array antenna design, and optimizes ICs for this application to help customers accelerate time to market. Advances in IC technology have enabled a shift in antenna technology, driving changes in multiple industries.