Symmetrical output three-way frequency circuit (74LS109, 74LS113)

The figure shows a three-way frequency division circuit with symmetrical output. When a conventional counter is used to divide a digital pulse into odd frequencies, even if the input is a symmetrical signal, the output cannot obtain a frequency division output with a duty cycle of 50%. The reason is that the internal trigger uses a unified rising edge (or falling edge) for triggering. In order to solve this problem, a JK trigger can be used, in which J and K are triggered by different clock edges, as shown in Figure (a). The circuit is composed of two JK triggers and an RS trigger. Its equivalent J terminal is triggered by CLH, and its equivalent K terminal is triggered by CLL. The rest of the functions are the same as those of a general JK trigger. Combining Figure (a) as a unit with a conventional D trigger and adding an inverter at the clock end can form a three-way frequency division circuit with symmetrical output, as shown in Figure (b). Figure (c) is a practical application circuit. Because the falling edge triggered 74LS113 is used in the figure, the inverter between it and the clock end of 74LS109 is omitted. The circuit 74LS109 and half of the 74LS113 form a circuit with the same function as Figure (a). The other half of the 74LS113 is equivalent to the D flip-flop in Figure (b).