single-ended input flip-flop
Source: InternetPublisher:smallembedded Keywords: flip-flop BSP pulse Updated: 2021/04/15
In the figure, two trigger signal input circuits are composed of = diode VD and Ri and cl.
cl is the acceleration capacitor.
When the input trigger pulse ua generates a positive spike pulse at point B, VD is cut off, causing the positive spike pulse to affect the trigger. Loss of triggering effect.
If the flip-flop shown in Figure 17-26 is in the l state (Q=1), that is, VT1 is saturated and VT2 is cut off, then inputting the trigger pulse "il" at the R end
will cause the flip-flop to transition to the 0 state. Therefore, the R end is called Set to end 0 or reset.
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