How should the DDR pins on the ZYNQ PS be connected to the DDR chip?

littleshrimp

How should the DDR pins on the ZYNQ PS be connected to the DDR chip? [Copy link]

I recently wanted to draw a ZYNQ board. I looked at other people's schematics and found that when the ZYNQ PS end is connected to the DDR chip, the DQx of the ZYNQ BANK 502 and the DQx of the DDR chip are not corresponding. As shown in the figure below, the DQ1 of the DDR chip is connected to DDR3_DQ5.

DDR3_DQ5 corresponds to the D1 pin of the FPGA, and the D1 pin is indeed DQ5.

I am confused about why the DQ1 of the DDR chip does not correspond to the DQ1 of the FPGA? Is there any other pattern? I have seen several schematics of others, and almost all of them are like this.

I only found the ug933 Zynq-7000 All Programmable SoC PCB Design Guide manual from Xilinx, but I didn't see any description on how to map the DQ pins.

walker2048

It doesn’t matter if the data is stored or retrieved incorrectly. The DQs in the same group can be changed at will. The main thing is to do it in a way that is convenient for wiring.

littleshrimp

walker2048 posted on 2024-7-24 12:58 It doesn’t matter if you store or retrieve the wrong data. You can change the DQ in the same group at will. The main thing is to do it in a way that is convenient for wiring.

I understand it now, thank you.

q1233

Thanks for sharing! Thanks for sharing! Thanks for sharing! Thanks for sharing! Thanks for sharing! Thanks for sharing! Thanks for sharing!