ZYNQ Antminer Board PS Side FreeRTOS+PL Side Light Test

tziang

ZYNQ Antminer Board PS Side FreeRTOS+PL Side Light Test [Copy link]

The previous article introduced the example program of the T9+ PL end light of the mining machine board. This article introduces the example program of the PS+PL end. The PS end runs a FreeRTOS hello world example, and the PL end flashes 4 LED lights.

Specific steps:

Open vivado and create a new project

Use default settings

Select the chip used by the mining board

The interface after the project is built

Start designing and create block designs

Add zynq processor IP to block design

Double-click the module to configure clock, DDR3, UART1, etc.

Configure two PL clocks, one of which is for the PL terminal

After the configuration is completed

Add LED flashing code on PL side

Named Blinkled

Write LED blinking code

Add LED flashing module to the block diagram design

Add PL clock connection and LED port

Add the PL port mapping constraints of the LED, and set the pin mapping of the 4 LED lights according to the schematic diagram

Convert the created block diagram design into top-level code

Top-level code structure

Generate bitstream

Exporting Hardware Design

Enable vitis (versions before 2019.2 are launch SDK, with similar functions and steps)

Create a new application

Select the xsa file just exported by vivado

Select freeRTOS and use the system

FreeRTOS version HELLO world example

Compile the application

Download bitstream

Download PS app

You can see the serial port output and the LED light on the board flashing

zynq2

zynq1

Theoretically, the B OOT.BIN generated after compilation is copied to the T card

The mining board can be set to boot from the SD card , but the board I have cannot boot. Is there a problem with the T card circuit on the board, or is other settings required? This needs further confirmation.

(Update: The generated BOOT.BIN can be directly copied to the T card to start. The previous failure to start was due to the wrong vivado export hardware. At the same time, you only need to modify the boot jumper mode, and R187 does not need to be modified)

Remove R187 to make MIO0 low level

At this point, the first complete usage example of the mining board PS +PL end is completed.

EPTmachine

The FPGA on-chip SOC system is very good for early chip verification.

bigbat

I remember that the chip on the ZYNQ mining machine has an A7 core and can run the Linux system, but the ZYNQ mining machine has been covered in dust. My mining machine has been changed to a 12V power supply and a diode has been added, but the power plug is hard to find.

qianniao29

bigbat posted on 2023-10-4 09:48 I remember that the chip on the ZYNQ mining machine has an A7 core and can run the Linux system, but the ZYNQ mining machine has been covered in dust. My mining machine...

The power plug is a 5557 interface

dongfeng_dream

The host is awesome